公开(公告)号：DE10202723A1

公开(公告)日：2003-04-03

申请号：DE10202723

申请日：2002-01-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STEIN VON KAMIENSKI ELARD ,  GEHRING OLIVER ,  STRENZ ROBERT ,  HAIBACH PATRICK ,  GEISSLER CHRISTIAN

IPC: G11C16/04 ,  H03K17/0812 ,  H03K17/08 ,  G11C7/24 ,  H03K17/16

Abstract: The circuit has a memory cell with a memory transistor and a switching transistor as a switch. The switching transistor's gate is connected to a memory cell output and the switching transistors is opened or closed according to the programming of the memory cell. A coupling transistor's source-drain path between the memory cell output and the switching transistor gate is opened or closed by applying a potential to the coupling transistor's gate. The circuit has a memory cell (10) with a memory transistor (M1) and a switching transistor (M4) as a switch (20) with a gate and a source-drain path controled by the gate voltage. The switching transistor's gate is connected to a memory cell output and the switching transistors is opened or closed according to the programming of the memory cell. A coupling transistor's (M3) source-drain path between the memory cell output and the switching transistor gate is opened or closed by applying a potential to the coupling transistor's gate.

公开(公告)号：DE10108923C1

公开(公告)日：2002-08-08

申请号：DE10108923

申请日：2001-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ABDUL-HAK AYAD ,  CASPARY DIRK ,  GRATZ ACHIM ,  HAIBACH PATRICK ,  KAMIENSKI ELARD STEIN VON ,  KUTTER CHRISTOPH

IPC: H01L21/762 ,  H01L29/78 ,  H01L21/336

公开(公告)号：DE10123362A1

公开(公告)日：2002-11-28

申请号：DE10123362

申请日：2001-05-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ABDUL-HAK AYAD ,  CASPARY DIRK ,  GRATZ ACHIM ,  HAIBACH PATRICK ,  KAMIENSKI ELARD STEIN VON ,  KUTTER CHRISTOPH

IPC: G01R31/3185 ,  H01L23/544 ,  H01L21/66

Abstract: The device has electronic chips and a memory device with a stored classification map with position and classification information for at least one part of the chip. The position information gives the position of each chip on the wafer and the classification information gives a classification of each chip in accordance with a given criterion. An Independent claim is also included for a wafer manufacturing method.

公开(公告)号：DE10114611A1

公开(公告)日：2002-10-17

申请号：DE10114611

申请日：2001-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STEIN VON KAMIENSKI ELARD ,  STRENZ ROBERT ,  BAUMGARTNER PETER ,  HAIBACH PATRICK ,  GEISSLER CHRISTIAN

IPC: G11C7/10 ,  G11C16/26

公开(公告)号：DE102004059636A1

公开(公告)日：2005-07-14

申请号：DE102004059636

申请日：2004-12-10

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES FLASH GM

Inventor： RIEDEL STEPHAN ,  SCHULZE NORBERT ,  HAIBACH PATRICK ,  HAUFE JUERG ,  KRATZERT PHILIPP ,  HABERKERN ROLAND

IPC: H01L21/336 ,  H01L29/78

Abstract: The method involves placing a structure with a gate contact (8) over a gate oxide layer (1) coated over a substrate (S). A silicon nitride layer (2) is laid over areas that are not covered by the structure. A spacer (3) made of tetra ethyl ortho silicate (TEOS) and placed on the nitride layer is etched to create a spacing of about 200 to 215 nanometer between the contact and a source region, and the contact and a drain region. An independent claim is also included for a semiconductor device with a MOS transistor having drain/source path.

公开(公告)号：DE10123362B4

公开(公告)日：2004-12-30

申请号：DE10123362

申请日：2001-05-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ABDUL-HAK AYAD ,  CASPARY DIRK ,  GRATZ ACHIM ,  HAIBACH PATRICK ,  KAMIENSKI ELARD STEIN VON ,  KUTTER CHRISTOPH

IPC: G01R31/3185 ,  H01L23/544 ,  H01L21/66

公开(公告)号：DE10259783A1

公开(公告)日：2004-07-15

申请号：DE10259783

申请日：2002-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PARASCANDOLA STEFANO ,  HABERKERN ROLAND ,  CASPARY DIRK ,  KNOEFLER ROMAN ,  HAUFE JUERG ,  KLEINT CHRISTOPH ,  SCHULZE NORBERT ,  POLEI VERONIKA ,  SACHSE JENS-UWE ,  DEPPE JOACHIM ,  RIEDEL STEPHAN ,  LUDWIG CHRISTOPH ,  HAIBACH PATRICK ,  STEIN VON KAMIENSKI ELARD

IPC: H01L21/8246 ,  H01L27/115 ,  H01L21/8247

Abstract: In first step specified insulation (5) is deposited on semiconductor substrate (1) and onto surface is applied memory layer stack of first boundary layer (2), memory layer (3) and second boundary layer (4). In second step, first conductivity doped troughs (6) are formed by mask technique and application of doping material into semiconductor substrate. In third step, opposite conductivity doped troughs (7) are formed by doping semiconductor substrate. By using the same mask, in second step at least second boundary layer in region (10) for first conductivity troughs is removed. By using the same mask, in third layer at least second boundary layer in region (11) for second conductivity troughs is removed.

公开(公告)号：DE10108924A1

公开(公告)日：2002-09-05

申请号：DE10108924

申请日：2001-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ABDUL-HAK AYAD ,  CASPARY DIRK ,  GRATZ ACHIM ,  HAIBACH PATRICK ,  KAMIENSKI ELARD STEIN VON ,  KUTTER CHRISTOPH

IPC: H01L21/66 ,  H01L23/544