中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.03 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE10349606A1

    公开(公告)日：2004-06-17

    申请号：DE10349606

    申请日：2003-10-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIETZ JAMES J ,  MA DAVID SUITWAI

    IPC: G11C29/48 ,  G11C29/00

    Abstract: A memory includes input/output paths and electrical leads. Each of the input/output paths are coupled to separate electrical leads. The memory is configured to operate in a test architecture and an operating architecture. In the test architecture, logic enables a greatest number of input/output paths. In the operating architecture, the memory enables the same or fewer input/output paths. The method of selecting a configuration includes establishing an operating and a test architecture and testing the memory in its greater input/output configuration.

    2.
    发明专利
    未知

    公开(公告)号：DE10337050A1

    公开(公告)日：2004-03-04

    申请号：DE10337050

    申请日：2003-08-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GERSTMEIER GUENTER ,  MA DAVID SUITWAI

    IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/082 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    Abstract: A DRAM memory unit contains a memory bit (mbit) transistor and a capacitive region for storing charge. The memory is configured to store data as a charge stored by the capacitive region. Each memory unit is accessed by an associated wordline and the data stored by the memory unit is read from an associated bitline connected to the memory unit. The memory units are connected to the associated wordline via a wordline contact and connected to the associated bitline via a bitline contact. The memory units are arranged in memory unit clusters that include multiple memory units having a common bitline contact. The wordline contact is configured to provide for orientation of the wordlines in the memory array independent of the orientation of the bitlines. The wordline contact is also configured to provide for at least one wordline layer separated from the memory unit by a height of the wordline contact. The wordline contact may be further configured to provide an upper wordline layer and a lower wordline layer each being above the bitline relative to the memory unit.

    5.
    发明专利
    未知

    公开(公告)号：DE10337033A1

    公开(公告)日：2004-03-25

    申请号：DE10337033

    申请日：2003-08-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIETZ JAMES J ,  MA DAVID SUITWAI ,  REN BING

    IPC: G01R1/04 ,  G11C5/04 ,  H01R4/38 ,  H01R33/76

    Abstract: An apparatus for mounting a semiconductor device to a circuit board for testing is disclosed. The semiconductor device includes semiconductor circuitry and leads to connect the semiconductor circuitry to the circuit board. Additionally, the semiconductor device is decapped so that at least a portion of the semiconductor circuitry is exposed. The apparatus includes a frame and a fastener. The frame is adapted to mate with the semiconductor device, and forms an opening for accessing the semiconductor circuitry and an edge surface for receiving the semiconductor device. The fastener is connected with the frame for removably connecting the frame to the circuit board. By using a frame instead of a socket, the distance to the semiconductor device once the device is mounted to the circuit board, and particularly the top side of the semiconductor device, can be reduced so that the device may be tested using a probe.

    6.
    发明专利
    未知

    公开(公告)号：DE102006004596A1

    公开(公告)日：2006-09-07

    申请号：DE102006004596

    申请日：2006-02-01

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MA DAVID SUITWAI ,  PARTSCH TORSTEN

    IPC: G11C11/4072

    Abstract: A power down is implemented in a memory device capable of performing a read operation in which data and a data strobe signal are supplied as outputs. The power down techniques includes generating a first signal for preventing the data from being supplied as an output of the memory device, generating a second signal for causing the data strobe signal to remain in a predetermined state, and generating a third signal for preventing the data strobe signal in the predetermined state from being supplied as an output of the memory device.

    7.
    发明专利
    未知

    公开(公告)号：DE10345481A1

    公开(公告)日：2004-04-22

    申请号：DE10345481

    申请日：2003-09-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MA DAVID SUITWAI ,  CHEN AIQIN

    IPC: G11C8/12 ,  G11C11/406 ,  G11C11/4097 ,  G11C11/4094

    Abstract: An integrated memory circuit and corresponding method for segmenting bit lines are provided, where the integrated memory circuit includes a sense amplifier, a layered bit line in signal communication with the sense amplifier, several segment pass transistors in signal communication with the layered bit line, several segmented bit lines, each in signal communication with a corresponding one of the several segment pass transistors, respectively, several memory cell pass transistors in signal communication with one of the several segmented bit lines, and a plurality of memory cell capacitors, each in signal communication with a corresponding one of the plurality of memory cell transistors, respectively; and where the corresponding method for segmenting bit lines includes receiving a memory cell address, activating a memory cell pass transistor with a wordline corresponding to the memory cell address, receiving a signal indicative of the memory cell charge level on a segmented bit line through the memory cell transistor, activating a segment pass transistor corresponding to the memory cell address, receiving a signal indicative of the memory cell charge level on a layered bit line through the segment pass transistor, and receiving a signal indicative of the memory cell charge level at the sense amplifier through the layered bit line.

    8.
    发明专利
    未知

    公开(公告)号：DE10334387A1

    公开(公告)日：2004-04-15

    申请号：DE10334387

    申请日：2003-07-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ALEXANDER GEORGE WILLIAM ,  BAKER STEVEN M ,  HUCKABY JENNIFER FAYE ,  MA DAVID SUITWAI

    IPC: G11C7/10 ,  G11C7/16 ,  G11C11/4096 ,  G11C11/4193 ,  G11C29/02 ,  G11C5/14

    Abstract: A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplexing circuit, the analog-to-digital converter sequentially connects to each voltage source and converts the measured voltage level of the source to a binary word. The interface circuit presents the binary word, e.g., serially, to test equipment off the integrated circuit.

Patent Agency Ranking