公开(公告)号：WO2004017143A3

公开(公告)日：2004-07-15

申请号：PCT/DE0302351

申请日：2003-07-11

Applicant: INFINEON TECHNOLOGIES AG ,  GOLLER KLAUS ,  HABERKERN ROLAND

Inventor： GOLLER KLAUS ,  HABERKERN ROLAND

IPC: G03F7/095 ,  G03F7/20 ,  H01L21/311 ,  H01L21/768 ,  G03F7/09

CPC classification number: H01L21/31144 ,  G03F7/095 ,  G03F7/203 ,  H01L21/76811 ,  H01L21/76813

Abstract: The invention relates to a method according to which a photosensitive resist layer arrangement (10) is produced after the production of a layer (12) to be structured, and is vertically selectively structured. Said resist layer arrangement contains, for example, a lower layer of lacquer (14) and an upper layer of lacquer (18). The inventive method enables less steps to be carried out during the production of an integrated circuit arrangement.

Abstract translation: 本发明涉及一种方法，其中在制造结构化层（12）之后，制造辐射敏感抗蚀剂层布置（10）并选择性地垂直构造。 抗蚀剂层结构包含例如下漆层（14）和上漆层（18）。 该方法可以节省制造集成电路装置中的工艺步骤。

公开(公告)号：DE102004062288B3

公开(公告)日：2006-07-13

申请号：DE102004062288

申请日：2004-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STEIN VON KAMIENSKI ELARD ,  RIEDEL STEPHAN ,  HABERKERN ROLAND ,  POLEI VERONIKA ,  KNOEFLER ROMAN ,  TEMPEL GEORG

IPC: H01L21/8247

Abstract: The method aims at improving the charge confinement of the memory layer at the edges facing the regions of buried bitlines. After the deposition of the memory layer between confinement layers and the implantation of dopants for bitlines and source/drain regions, an oxidation of semiconductor material to form upper bitline isolation regions takes place. By this method, additional oxide regions are produced at the edges of the memory layer in the same oxidation step. Either a silicon layer may be deposited and reduced to sidewall spacers, which are subsequently oxidized; or recesses are etched into the memory layer and subsequently filled with semiconductor oxide.

公开(公告)号：DE102004059636A1

公开(公告)日：2005-07-14

申请号：DE102004059636

申请日：2004-12-10

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES FLASH GM

Inventor： RIEDEL STEPHAN ,  SCHULZE NORBERT ,  HAIBACH PATRICK ,  HAUFE JUERG ,  KRATZERT PHILIPP ,  HABERKERN ROLAND

IPC: H01L21/336 ,  H01L29/78

Abstract: The method involves placing a structure with a gate contact (8) over a gate oxide layer (1) coated over a substrate (S). A silicon nitride layer (2) is laid over areas that are not covered by the structure. A spacer (3) made of tetra ethyl ortho silicate (TEOS) and placed on the nitride layer is etched to create a spacing of about 200 to 215 nanometer between the contact and a source region, and the contact and a drain region. An independent claim is also included for a semiconductor device with a MOS transistor having drain/source path.

公开(公告)号：DE10259783A1

公开(公告)日：2004-07-15

申请号：DE10259783

申请日：2002-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PARASCANDOLA STEFANO ,  HABERKERN ROLAND ,  CASPARY DIRK ,  KNOEFLER ROMAN ,  HAUFE JUERG ,  KLEINT CHRISTOPH ,  SCHULZE NORBERT ,  POLEI VERONIKA ,  SACHSE JENS-UWE ,  DEPPE JOACHIM ,  RIEDEL STEPHAN ,  LUDWIG CHRISTOPH ,  HAIBACH PATRICK ,  STEIN VON KAMIENSKI ELARD

IPC: H01L21/8246 ,  H01L27/115 ,  H01L21/8247

Abstract: In first step specified insulation (5) is deposited on semiconductor substrate (1) and onto surface is applied memory layer stack of first boundary layer (2), memory layer (3) and second boundary layer (4). In second step, first conductivity doped troughs (6) are formed by mask technique and application of doping material into semiconductor substrate. In third step, opposite conductivity doped troughs (7) are formed by doping semiconductor substrate. By using the same mask, in second step at least second boundary layer in region (10) for first conductivity troughs is removed. By using the same mask, in third layer at least second boundary layer in region (11) for second conductivity troughs is removed.

公开(公告)号：DE10233209A1

公开(公告)日：2004-02-05

申请号：DE10233209

申请日：2002-07-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLLER KLAUS ,  HABERKERN ROLAND

IPC: G03F7/095 ,  G03F7/20 ,  H01L21/311 ,  H01L21/768

Abstract: Irradiating a resist during the production of an integrated switching arrangement comprises forming a radiation-sensitive resist layer arrangement (10) after producing a layer (12) to be structured, and irradiating the resist layer arrangement using a radiation source. During irradiation the structure of a region (40-44) close to the radiation source is changed in such a way that the region is selectively developed and the structure of a region (46-50) of the resist layer arrangement away from the radiation source covered by the region close to the radiation source is only slightly changed.