公开(公告)号：JP2006245579A

公开(公告)日：2006-09-14

申请号：JP2006051536

申请日：2006-02-28

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： WILLER JOSEF ,  MIKOLAJICK THOMAS ,  LUDWIG CHRISTOPH ,  SCHULZE NORBERT ,  KUESTERS KARL HEINZ

IPC: H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7923

Abstract: PROBLEM TO BE SOLVED: To provide a memory having a charge trap memory cell, and a forming method of the memory having the trap memory cell.
SOLUTION: The semiconductor memory is characterized in that a current direction of each channel region of a memory transistor is a longitudinal direction with respect to a related word line 3, in that a bit line 2 is arranged on a top surface of the word line so that it may be electrically insulated from the word line 3, in that a local interconnection 4, which is electrically conductive, of source/drain regions is prepared, in that the local interconnection 4 is arranged in a spacing zone between the above-mentioned word lines 3 so that it may be electrically insulated from the word line 3, and connected to the above-mentioned bit line 2 simultaneously, and in that a gate electrode is arranged within a trench at least partially formed inside a memory substrate.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有电荷陷阱存储单元的存储器，以及具有陷阱存储单元的存储器的形成方法。 解决方案：半导体存储器的特征在于，存储晶体管的每个沟道区域的电流方向是相对于相关字线3的纵向方向，因为位线2被布置在 字线，使得其可以与字线3电绝缘，因为制备了源/漏区的导电的局部互连4，其中局部互连4布置在上述之间的间隔区域中 所述字线3可以与字线3电绝缘，并且同时连接到上述位线2，并且栅极布置在至少部分地形成在存储器基板内部的沟槽内。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：DE102004059636A1

公开(公告)日：2005-07-14

申请号：DE102004059636

申请日：2004-12-10

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES FLASH GM

Inventor： RIEDEL STEPHAN ,  SCHULZE NORBERT ,  HAIBACH PATRICK ,  HAUFE JUERG ,  KRATZERT PHILIPP ,  HABERKERN ROLAND

IPC: H01L21/336 ,  H01L29/78

Abstract: The method involves placing a structure with a gate contact (8) over a gate oxide layer (1) coated over a substrate (S). A silicon nitride layer (2) is laid over areas that are not covered by the structure. A spacer (3) made of tetra ethyl ortho silicate (TEOS) and placed on the nitride layer is etched to create a spacing of about 200 to 215 nanometer between the contact and a source region, and the contact and a drain region. An independent claim is also included for a semiconductor device with a MOS transistor having drain/source path.

公开(公告)号：DE10259783A1

公开(公告)日：2004-07-15

申请号：DE10259783

申请日：2002-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PARASCANDOLA STEFANO ,  HABERKERN ROLAND ,  CASPARY DIRK ,  KNOEFLER ROMAN ,  HAUFE JUERG ,  KLEINT CHRISTOPH ,  SCHULZE NORBERT ,  POLEI VERONIKA ,  SACHSE JENS-UWE ,  DEPPE JOACHIM ,  RIEDEL STEPHAN ,  LUDWIG CHRISTOPH ,  HAIBACH PATRICK ,  STEIN VON KAMIENSKI ELARD

IPC: H01L21/8246 ,  H01L27/115 ,  H01L21/8247

Abstract: In first step specified insulation (5) is deposited on semiconductor substrate (1) and onto surface is applied memory layer stack of first boundary layer (2), memory layer (3) and second boundary layer (4). In second step, first conductivity doped troughs (6) are formed by mask technique and application of doping material into semiconductor substrate. In third step, opposite conductivity doped troughs (7) are formed by doping semiconductor substrate. By using the same mask, in second step at least second boundary layer in region (10) for first conductivity troughs is removed. By using the same mask, in third layer at least second boundary layer in region (11) for second conductivity troughs is removed.

公开(公告)号：DE102005004146A1

公开(公告)日：2006-06-01

申请号：DE102005004146

申请日：2005-01-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZE NORBERT ,  RIEDEL STEPHAN ,  STEIN VON KAMIENSKI ELARD

IPC: G11C16/04

Abstract: The memory has a substrate (1) with a substrate region, and electrically insulating units disposed in the substrate. Wells (2) of a doping type is disposed in the substrate, and a set of non-volatile memory cells is arranged in a set of sectors. A word line electrically connects memory cells of a group of sectors. A set of switching units connect the respective wells to a word line potential. An independent claim is also included for a method for operating a non-volatile semiconductor memory.

公开(公告)号：DE102005014507A1

公开(公告)日：2006-09-07

申请号：DE102005014507

申请日：2005-03-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WILLER JOSEF ,  MIKOLAJICK THOMAS ,  LUDWIG CHRISTOPH ,  SCHULZE NORBERT ,  KUESTERS KARL-HEINZ

IPC: H01L27/115 ,  H01L21/8247