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公开(公告)号：DE10322541A1
公开(公告)日：2004-12-16
申请号：DE10322541
申请日：2003-05-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： PROELL MANFRED , STAVROU EVANGELOS , SCHNEIDER RALF , HARTNER TOBIAS
Abstract: The memory chip has an integral address scrambling unit (22,23) which has address inputs for entering an address. The address scrambling unit is arranged and adapted such that the addresses can be scrambled differently dependent on the control bits. A memory cell field is provided and is connected to the output of the address scrambling unit. The scrambling unit may have several predefined scramblers for scrambling the addresses in different ways. Independent claims also cover a method of scrambling addresses.
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公开(公告)号：DE10110272B4
公开(公告)日：2004-10-14
申请号：DE10110272
申请日：2001-03-02
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HARTNER TOBIAS , FOERSTE MARKUS , WIRTH NORBERT
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公开(公告)号：DE10104716C2
公开(公告)日：2003-03-20
申请号：DE10104716
申请日：2001-02-02
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HARTNER TOBIAS , LUKAS RUPERT , WIRTH NORBERT
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Patent Agency Ranking
公开(公告)号：DE10131277A1
公开(公告)日：2003-01-16
申请号：DE10131277
申请日：2001-06-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHNEIDER RALF , WIRTH NORBERT , STAVROU EVANGELOS , HARTNER TOBIAS
Abstract: A process for address coding a semiconductor memory device comprises forming the device with a memory cell field with physical and electrical X:Y addresses. A physical address of a given cell is placed in an address installing device and decoded in an address decoding device (18) in its decoding mode. An Independent claim is also included for a semiconductor device for the above process.
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公开(公告)号：DE10308924B3
公开(公告)日：2004-10-28
申请号：DE10308924
申请日：2003-02-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHROEDER STEPHAN , HARTNER TOBIAS , VOLLRATH JOERG
IPC: H01L21/768 , H01L21/8242 , H01L23/528 , H01L27/02 , H01L27/108
Abstract: An integrated semiconductor circuit can have memory cells, which can be read by word lines and bit lines. Two mutually adjacent bit lines in each case are connected to inputs of the same signal amplifier. In order to compensate for parasitic capacitors, which arise at thin sidewall insulations between the patterned word lines and adjacent bit line contacts, additional contact structures which lead past the word lines and represent dummy contacts can be provided. The additional parasitic capacitances produced by the dummy contact alter the electrical potential of the respective reference bit line at the signal amplifier like the parasitic capacitances of activated bit lines, as a result of which the measured differential potential can be corrected with respect to the parasitic effects.
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公开(公告)号：DE10308872B3
公开(公告)日：2004-08-19
申请号：DE10308872
申请日：2003-02-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HARTNER TOBIAS , SCHROEDER STEPHAN , VOLLRATH JOERG
IPC: G11C7/00 , H01L21/8242 , H01L23/528 , H01L27/108
Abstract: The memory circuit (10) has a memory cell field with a number of memory cells, each having a selection transistor and a memory capacitor, controlled via bit lines (1) and word lines (2). The memory capacitors, the bit lines and the word lines are arranged in different planes in a semiconductor substrate, with contact structures (3) at the word line level for connecting the bit lines with the selection transistors, each 2 bit lines coupled to a common signal amplifier (30). At least 2 additional word lines (11,12) and associated blind contact structures (13) are used for compensation of parasitic capacitances.
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公开(公告)号：DE10110272A1
公开(公告)日：2002-09-19
申请号：DE10110272
申请日：2001-03-02
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HARTNER TOBIAS , FOERSTE MARKUS , WIRTH NORBERT
Abstract: The semiconductor memory has a random number generator (20) providing random number values in parallel for the memory banks (11,12,13,14) of the memory cell field (10), with comparison of the entered data values read out from the different memory banks, for allowing a fault signal to be provided.
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公开(公告)号：DE10104716A1
公开(公告)日：2002-08-29
申请号：DE10104716
申请日：2001-02-02
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HARTNER TOBIAS , LUKAS RUPERT , WIRTH NORBERT
Abstract: A method of testing a semiconductor memory in which the semiconductor memory is off-set into a test drive and an oscillator (207) arranged in the semiconductor memory is released, and depending on the oscillator, a variable voltage (VPP, VINT,VBLEQ,VBLH,VPL,VBB) is generated and a function test of the memory cells (101,119) is carried out.
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