公开(公告)号：DE102004047058B4

公开(公告)日：2006-12-21

申请号：DE102004047058

申请日：2004-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BENZINGER HERBERT ,  PROELL MANFRED ,  SCHNEIDER RALF ,  SCHROEDER STEPHAN

IPC: G11C8/08 ,  G11C29/02

公开(公告)号：DE10259055B4

公开(公告)日：2006-11-16

申请号：DE10259055

申请日：2002-12-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER RALF ,  SCHROEDER STEPHAN ,  PROELL MANFRED ,  VOLLRATH JOERG

IPC: G05F1/46 ,  G11C11/4074 ,  H02M3/07

公开(公告)号：DE102004047058A1

公开(公告)日：2006-04-06

申请号：DE102004047058

申请日：2004-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BENZINGER HERBERT ,  PROELL MANFRED ,  SCHNEIDER RALF ,  SCHROEDER STEPHAN

IPC: G11C8/08 ,  G11C29/02

Abstract: Word wires (WL) can be linked to a first voltage potential (VWL) via first (11) and third (13) controllable switches (CS) and to a second voltage potential (VPP) via a second CS (12). After conductive control of each first and third CS, each second CS is conductively controlled in a test operating condition for an integrated semiconductor memory. An independent claim is also included for a method for testing an integrated semiconductor memory.

公开(公告)号：DE102004017284A1

公开(公告)日：2005-10-27

申请号：DE102004017284

申请日：2004-04-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CAMPENHAUSEN AUREL VON ,  GNAT MARCIN ,  VOLLRATH JOERG ,  SCHNEIDER RALF

IPC: G11C29/12 ,  H01L21/66 ,  H01L23/58 ,  H01L27/108 ,  H02H9/04

Abstract: Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.

公开(公告)号：DE10258168B4

公开(公告)日：2005-07-07

申请号：DE10258168

申请日：2002-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PROELL MANFRED ,  SCHROEDER STEPHAN ,  SCHNEIDER RALF ,  KLIEWER JOERG

IPC: G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/12

Abstract: Local data lines (LDQT,LDQC) segmented as a column (Y) can each be linked in read/write cycles by a column-select line (CSL) switch (3) to primary sense amplifiers for delivering widened data signals to and from bit lines (BLT,BLC) in each segment (I,II,III). The CSL switch points to a column select signal supplied over a CSL running in a line direction (X). An Independent claim is also included for a method for operating an integrated semiconductor memory acting as dynamic random access memory (DRAM).

公开(公告)号：DE102004012630A1

公开(公告)日：2005-06-30

申请号：DE102004012630

申请日：2004-03-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOLLRATH JOERG ,  GNAT MARCIN ,  SCHNEIDER RALF ,  SCHROEDER STEFAN

IPC: H01L21/336 ,  H01L21/8242 ,  H01L29/08 ,  H01L29/78 ,  H01L27/105

Abstract: A FET comprises a source (42a), a drain (42b) and a canal region (46) in a substrate (10). The source and/or drain regions are separated from the canal region by a barrier layer (40). The latter consists of a nitride or oxide layer.

公开(公告)号：DE10059553B4

公开(公告)日：2005-04-28

申请号：DE10059553

申请日：2000-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER RALF ,  WIRTH NORBERT ,  BENZINGER HERBERT

IPC: G11C7/10 ,  G11C7/22

Abstract: A circuit configuration and a method for the synchronization of signals include transmitting signals in parallel through data lines and buffer-storing the signals in a synchronizing unit. A clock signal is determined from the signals of a data line and is used for synchronizing the outputting of the signals. The signals are output in the order in which the signals were read. The signals are likewise output through a plurality of data lines, the signals being output temporally synchronously. Propagation time differences are compensated due to the buffer-storage. Moreover, the clock signal is determined from the signals themselves. Consequently, the use of an additional clock signal is not necessary.

公开(公告)号：DE10316579A1

公开(公告)日：2004-11-04

申请号：DE10316579

申请日：2003-04-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GNAT MARCIN ,  SCHNEIDER RALF ,  VOLLRATH JOERG

IPC: G11C7/10 ,  H03K19/00 ,  H03K19/0175

公开(公告)号：DE10302650A1

公开(公告)日：2004-08-12

申请号：DE10302650

申请日：2003-01-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PROELL MANFRED ,  SCHROEDER STEPHAN ,  SCHNEIDER RALF ,  KLIEWER JOERG

IPC: G11C7/12 ,  G11C7/18 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4091

Abstract: RAM memory with shared SA structure, wherein a short circuit transistor (30) is connected, for all bit transfer line pairs connected to a sense amplifier (SA), to the sense amplifier and can be separately switched for each individual control line (9) using a short circuit control signal. An independent claim is made for a control method for a RAM memory with shared SA structure.

公开(公告)号：DE10131277A1

公开(公告)日：2003-01-16

申请号：DE10131277

申请日：2001-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER RALF ,  WIRTH NORBERT ,  STAVROU EVANGELOS ,  HARTNER TOBIAS

IPC: G11C29/18 ,  G11C29/36 ,  G11C29/00

Abstract: A process for address coding a semiconductor memory device comprises forming the device with a memory cell field with physical and electrical X:Y addresses. A physical address of a given cell is placed in an address installing device and decoded in an address decoding device (18) in its decoding mode. An Independent claim is also included for a semiconductor device for the above process.