2.
    发明专利
    未知

    公开(公告)号:DE10039350A1

    公开(公告)日:2002-02-28

    申请号:DE10039350

    申请日:2000-08-11

    Abstract: An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only once, so that subsequent writing to the particular memory cells is blocked. The circuit is used in a test structure for integrated circuits on a wafer. A method for testing integrated circuits on a wafer that are connected to a test apparatus is also described. Once the supply voltage to a first circuit to be tested has been turned on, a preliminary test is carried out to ascertain parameters that need to be set. The supply voltage is then applied to a next circuit to be tested, a preliminary test is carried out, and memory cells have information written to them, until the parameters have been set for all the connected circuits to be tested. The test apparatus then carries out the actual operational test in parallel for all the connected circuits to be tested.

    4.
    发明专利
    未知

    公开(公告)号:DE59811858D1

    公开(公告)日:2004-09-30

    申请号:DE59811858

    申请日:1998-06-04

    Abstract: The circuit arrangement includes a device (10) for generating digital signals, with a voltage connection (8) for the supply of an external reference voltage to the device, and a voltage generator (2) for the production of an internal reference voltage which is supplied to the device over a switch (4). A level converter (6) is provided for the control of the switch, whereby a switch signal for the switching of the switch is raised on a level lying above the switching threshold of the switch. An output coupling capacitor (C1) is connected between the output of the voltage generator and a first supply voltage (VSS).

    10.
    发明专利
    未知

    公开(公告)号:DE10059553B4

    公开(公告)日:2005-04-28

    申请号:DE10059553

    申请日:2000-11-30

    Abstract: A circuit configuration and a method for the synchronization of signals include transmitting signals in parallel through data lines and buffer-storing the signals in a synchronizing unit. A clock signal is determined from the signals of a data line and is used for synchronizing the outputting of the signals. The signals are output in the order in which the signals were read. The signals are likewise output through a plurality of data lines, the signals being output temporally synchronously. Propagation time differences are compensated due to the buffer-storage. Moreover, the clock signal is determined from the signals themselves. Consequently, the use of an additional clock signal is not necessary.

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