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公开(公告)号:DE10152916A1
公开(公告)日:2003-05-22
申请号:DE10152916
申请日:2001-10-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor: STOCKEN CHRISTIAN , CORDES ERIC , WIRTH NORBERT , TASKIN NAZIF
Abstract: The module (52) incorporating an EEPROM, has an information containing unit (56) that contains information relating to the memory module. A memory chip (54) arranged on the memory module has the information containing unit arranged in a distributed way. The information containing unit has flip flops for permanently programming information that relates to operational parameters of the memory module.
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公开(公告)号:DE10039350A1
公开(公告)日:2002-02-28
申请号:DE10039350
申请日:2000-08-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SCHNEIDER RALF , WIRTH NORBERT , GRUBER ARNDT , RUF BERNHARD
IPC: G01R31/3177 , G11C7/00 , G11C29/00 , H01L21/66 , H01L31/0328
Abstract: An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only once, so that subsequent writing to the particular memory cells is blocked. The circuit is used in a test structure for integrated circuits on a wafer. A method for testing integrated circuits on a wafer that are connected to a test apparatus is also described. Once the supply voltage to a first circuit to be tested has been turned on, a preliminary test is carried out to ascertain parameters that need to be set. The supply voltage is then applied to a next circuit to be tested, a preliminary test is carried out, and memory cells have information written to them, until the parameters have been set for all the connected circuits to be tested. The test apparatus then carries out the actual operational test in parallel for all the connected circuits to be tested.
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公开(公告)号:DE10152916B4
公开(公告)日:2006-11-30
申请号:DE10152916
申请日:2001-10-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor: STOCKEN CHRISTIAN , CORDES ERIC , WIRTH NORBERT , TASKIN NAZIF
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公开(公告)号:DE59811858D1
公开(公告)日:2004-09-30
申请号:DE59811858
申请日:1998-06-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SICHERT CHRISTIAN , KAISER ROBERT , WIRTH NORBERT
IPC: H03K5/02 , H03K5/08 , H03K17/14 , H03K17/687 , H03K19/0185
Abstract: The circuit arrangement includes a device (10) for generating digital signals, with a voltage connection (8) for the supply of an external reference voltage to the device, and a voltage generator (2) for the production of an internal reference voltage which is supplied to the device over a switch (4). A level converter (6) is provided for the control of the switch, whereby a switch signal for the switching of the switch is raised on a level lying above the switching threshold of the switch. An output coupling capacitor (C1) is connected between the output of the voltage generator and a first supply voltage (VSS).
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公开(公告)号:DE10161044A1
公开(公告)日:2003-03-13
申请号:DE10161044
申请日:2001-12-12
Applicant: INFINEON TECHNOLOGIES AG
Inventor: STOCKEN CHRISTIAN , CORDES ERIC , WIRTH NORBERT , TASKIN NAZIF
IPC: H01L23/525 , H01L23/58
Abstract: An integrated semiconductor chip comprises a substrate (1) with a circuit (3) contact surfaces (4) connected to a chip housing (5) connections (6). An electrically switchable device (7) in a connection between the circuit and housing can be switched in to select one of many operational modes of the chip.
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公开(公告)号:DE10110272A1
公开(公告)日:2002-09-19
申请号:DE10110272
申请日:2001-03-02
Applicant: INFINEON TECHNOLOGIES AG
Inventor: HARTNER TOBIAS , FOERSTE MARKUS , WIRTH NORBERT
Abstract: The semiconductor memory has a random number generator (20) providing random number values in parallel for the memory banks (11,12,13,14) of the memory cell field (10), with comparison of the entered data values read out from the different memory banks, for allowing a fault signal to be provided.
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公开(公告)号:DE10104716A1
公开(公告)日:2002-08-29
申请号:DE10104716
申请日:2001-02-02
Applicant: INFINEON TECHNOLOGIES AG
Inventor: HARTNER TOBIAS , LUKAS RUPERT , WIRTH NORBERT
Abstract: A method of testing a semiconductor memory in which the semiconductor memory is off-set into a test drive and an oscillator (207) arranged in the semiconductor memory is released, and depending on the oscillator, a variable voltage (VPP, VINT,VBLEQ,VBLH,VPL,VBB) is generated and a function test of the memory cells (101,119) is carried out.
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公开(公告)号:DE10058324A1
公开(公告)日:2002-06-13
申请号:DE10058324
申请日:2000-11-24
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SCHNEIDER RALF , WIRTH NORBERT , BENZINGER HERBERT
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公开(公告)号:DE10355333B3
公开(公告)日:2005-06-30
申请号:DE10355333
申请日:2003-11-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: EGGERS GEORG , WIRTH NORBERT , BENZINGER HERBERT , HUBER THOMAS
Abstract: The invention relates to a method and a device ( 1, 11, 21 ) for detecting the overheating of a semiconductor device, comprising a temperature measuring means ( 3, 13, 23 ) that changes its electrical conductivity when the temperature of the semiconductor device changes.
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公开(公告)号:DE10059553B4
公开(公告)日:2005-04-28
申请号:DE10059553
申请日:2000-11-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SCHNEIDER RALF , WIRTH NORBERT , BENZINGER HERBERT
Abstract: A circuit configuration and a method for the synchronization of signals include transmitting signals in parallel through data lines and buffer-storing the signals in a synchronizing unit. A clock signal is determined from the signals of a data line and is used for synchronizing the outputting of the signals. The signals are output in the order in which the signals were read. The signals are likewise output through a plurality of data lines, the signals being output temporally synchronously. Propagation time differences are compensated due to the buffer-storage. Moreover, the clock signal is determined from the signals themselves. Consequently, the use of an additional clock signal is not necessary.
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