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公开(公告)号:WO2004075197A3
公开(公告)日:2005-03-03
申请号:PCT/EP2004050207
申请日:2004-01-14
Applicant: INFINEON TECHNOLOGIES AG , STAVROU EVANGELOS , PROELL MANFRED , SCHROEDER STEPHAN , KLIEWER JOERG
Inventor: STAVROU EVANGELOS , PROELL MANFRED , SCHROEDER STEPHAN , KLIEWER JOERG
CPC classification number: G11C11/15
Abstract: The invention relates to an MRAM memory cell in which the magnetic layers (ML1, ML2) separated by an intermediate layer (ZS) are made at least in part of a ferromagnetic material.
Abstract translation: 本发明涉及一种MRAM存储单元,其特征在于,通过一个中间层(ZS)分开磁性层(ML1,ML2)所述至少部分由铁磁材料构成。
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公开(公告)号:DE10302224B4
公开(公告)日:2007-09-13
申请号:DE10302224
申请日:2003-01-20
Applicant: INFINEON TECHNOLOGIES AG
Inventor: PROELL MANFRED , SCHROEDER STEPHAN , STAVROU EVANGELOS , NEUBAUER HEINZ-JOACHIM
IPC: G11C11/4097 , G11C7/12 , G11C11/4094
Abstract: An integrated memory has a memory cell array having word lines and bit lines. The bit lines are organized in bit line pairs. The bit lines of the bit line pairs cross one another at a crossing location and run parallel to one another. A sense amplifier is connected to one of the bit line pairs at one end. Two precharge circuits are provided. One precharge circuit is arranged on a side of the crossing location and the other precharge circuit is arranged on a side of the crossing location. The precharge circuit facing the sense amplifier is arranged at a first distance from the crossing location and at a second distance from the sense amplifier. The RC constant of the bit lines, which is effective during the precharge operation, is reduced, so that the time period required for a precharge operation is reduced.
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公开(公告)号:DE102004042338B4
公开(公告)日:2006-09-07
申请号:DE102004042338
申请日:2004-09-01
Applicant: INFINEON TECHNOLOGIES AG
Inventor: STAVROU EVANGELOS , WIRKER BJOERN , GRUBER ARNDT
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公开(公告)号:DE102004042338A1
公开(公告)日:2006-03-09
申请号:DE102004042338
申请日:2004-09-01
Applicant: INFINEON TECHNOLOGIES AG
Inventor: STAVROU EVANGELOS , WIRKER BJOERN , GRUBER ARNDT
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公开(公告)号:DE10322541A1
公开(公告)日:2004-12-16
申请号:DE10322541
申请日:2003-05-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor: PROELL MANFRED , STAVROU EVANGELOS , SCHNEIDER RALF , HARTNER TOBIAS
Abstract: The memory chip has an integral address scrambling unit (22,23) which has address inputs for entering an address. The address scrambling unit is arranged and adapted such that the addresses can be scrambled differently dependent on the control bits. A memory cell field is provided and is connected to the output of the address scrambling unit. The scrambling unit may have several predefined scramblers for scrambling the addresses in different ways. Independent claims also cover a method of scrambling addresses.
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公开(公告)号:DE10323865B4
公开(公告)日:2005-04-21
申请号:DE10323865
申请日:2003-05-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor: ZANDEN KOEN VAN DER , STAVROU EVANGELOS , PROELL MANFRED , SCHROEDER STEPHAN
Abstract: An integrated circuit, in particular, an integrated memory, contains a control circuit for ascertaining an operating state of the circuit. A self-repair circuit, which is connected to the control circuit, is used to implement self-test and self-repair operation for checking the functioning of, and repairing, defective circuit sections of the integrated circuit. After a supply voltage has been applied to the integrated circuit, the control circuit ascertains an operating state of the integrated circuit and, in a manner dependent thereon, the self-repair circuit is activated by the control circuit in a self-controlling manner in order to put the integrated circuit into a self-repair mode for implementing self-test and self-repair operation. The integrated circuit can be tested for its functionality and repaired even after being soldered onto a module substrate.
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公开(公告)号:DE10313605A1
公开(公告)日:2004-10-21
申请号:DE10313605
申请日:2003-03-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor: EGGERS GEORG ERHARD , STAVROU EVANGELOS , PROELL MANFRED
Abstract: The device according to the invention in each case has a temperature sensor for detecting the temperatures of the memory modules, which is arranged in the memory modules. In addition, a memory control module is provided, which, in order to evaluate the temperatures, is connected to the memory modules via a measurer or means for determining the highest operating temperature of the memory modules. The memory control module is designed and can be operated such that an adaptation operation is initiated, if the highest operating temperature exceeds a specific value.
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公开(公告)号:DE10301092A1
公开(公告)日:2004-07-29
申请号:DE10301092
申请日:2003-01-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor: STAVROU EVANGELOS , PROELL MANFRED , SCHROEDER STEPHAN , KLIEWER JOERG
Abstract: A magnetic RAM memory (MRAM) comprises two magnetic layers (ML1,ML2) one hard magnetic and the other soft, separated by a nonmagnetic layer (ZS) so that information can be stored according to the relative magnetizing condition of the soft layer with respect to the hard layer. At least one magnetic layer comprises ferromagnetic material.
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公开(公告)号:DE10131277A1
公开(公告)日:2003-01-16
申请号:DE10131277
申请日:2001-06-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SCHNEIDER RALF , WIRTH NORBERT , STAVROU EVANGELOS , HARTNER TOBIAS
Abstract: A process for address coding a semiconductor memory device comprises forming the device with a memory cell field with physical and electrical X:Y addresses. A physical address of a given cell is placed in an address installing device and decoded in an address decoding device (18) in its decoding mode. An Independent claim is also included for a semiconductor device for the above process.
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公开(公告)号:DE10301092B4
公开(公告)日:2006-06-29
申请号:DE10301092
申请日:2003-01-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor: STAVROU EVANGELOS , PROELL MANFRED , SCHROEDER STEPHAN , KLIEWER JOERG
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