公开(公告)号：WO2005043623A2

公开(公告)日：2005-05-12

申请号：PCT/EP2004052594

申请日：2004-10-20

Applicant: INFINEON TECHNOLOGIES AG ,  GSCHWANDTNER ALEXANDER ,  HOLZ JUERGEN ,  SCHRENK MICHAEL

Inventor： GSCHWANDTNER ALEXANDER ,  HOLZ JUERGEN ,  SCHRENK MICHAEL

IPC: C23C14/06 ,  C23C16/34 ,  C23C16/44 ,  C23C16/455 ,  C23C16/511 ,  H01L21/02 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L27/08

CPC classification number: C23C16/45542 ,  C23C16/345 ,  C23C16/45523 ,  C23C16/511 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76807 ,  H01L23/5223 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a method that permits the direct application of a dielectric layer to a metallic layer containing copper. According to said method, two process gases (26, 28) are excited by means of respectively different plasma powers for each substrate surface or one of the process gases (26) is excited by means of a plasma and the other process gas (28) is not excited.

Abstract translation: 解释措施，除其他外， 允许电介质层的上的含铜金属的直接应用。 因此，两种处理气体是（26,28），兴奋与每个衬底表面相互不同的等离子体功率或处理气体（26）被激发的等离子和其它工艺气体（28）不被激励。

公开(公告)号：DE50114869D1

公开(公告)日：2009-06-10

申请号：DE50114869

申请日：2001-03-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LACHNER RUDOLF ,  SCHWERD MARKUS ,  SCHRENK MICHAEL

IPC: H01G4/33 ,  H01L21/02 ,  H01L29/92 ,  H01L23/522

Abstract: The integrated component has a number of conductor paths (13) and a capacitor (12) with a dielectric layer (5) between 2 electrode layers (14,15), which together are provided using the same sequence of metallisation layers (3,4,7-11) as that for the adjacent conductor path. The capacitor electrode layers may each be coupled to an underlying or overlying metal conductor path layer via a perpendicular connection (2,16), e.g. formed in an underlying intermediate dielectric layer (1).

公开(公告)号：DE10350752A1

公开(公告)日：2005-06-09

申请号：DE10350752

申请日：2003-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHRENK MICHAEL ,  HOLZ JUERGEN ,  GSCHWANDTNER ALEXANDER

IPC: C23C14/06 ,  C23C16/34 ,  C23C16/44 ,  C23C16/455 ,  C23C16/511 ,  H01L21/02 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L27/08 ,  H01L21/822 ,  H01L21/314

Abstract: Process for forming a dielectric. The process may include forming the dielectric on a metallization and capacitor arrangement. The process allows the direct application of a dielectric layer to a copper-containing metallization. Accordingly, two process gases may be excited with different plasma powers per unit substrate area, or one process gas may be excited with a plasma and another process gas may not be excited.

公开(公告)号：DE102007019811B4

公开(公告)日：2014-11-27

申请号：DE102007019811

申请日：2007-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GLAS ALEXANDER ,  HARTUNG WOLFGANG DR ,  SCHRENK MICHAEL ,  KLEIN WOLFGANG DR RER NAT ,  KEBINGER HERBERT

IPC: H01L27/06 ,  H01F17/00 ,  H01L23/488 ,  H01L23/60 ,  H01L23/64 ,  H03H7/01

Abstract: Schaltung (100; 200) mit: einem Eingangskontakt (110; 210) und einem Ausgangskontakt (212) zum elektrischen Anschließen der Schaltung (100; 200); einem ersten Schaltungselement (130; D1; D11), wobei ein erster Anschluss (132) des ersten Schaltungselements (130; D1; D11) mit dem Eingangskontakt (110; 210) elektrisch gekoppelt ist; und einer ersten Spule (120; L1; L11), die um den Eingangskontakt (110; 210) und das erste Schaltungselement (130; D1; D11) herum angeordnet ist, wobei ein innen liegender Spulenanschluss (122; 322) der ersten Spule (120; L1; L11), der in der ersten Spule (120; L1; L11) angeordnet ist, mit dem Eingangskontakt (110) elektrisch gekoppelt ist, und ein außen liegender Spulenanschluss (124; 324) der ersten Spule (120; L1; L11), der außerhalb der ersten Spule (120; L1; L11) angeordnet ist, mit dem Ausgangskontakt (212) elektrisch gekoppelt ist, wobei das erste Schaltungselement (130; D1; D11) eine ESD-Diode zum Schutz der Schaltung (100; 200) vor elektrostatischer Entladung ist.

公开(公告)号：AT430380T

公开(公告)日：2009-05-15

申请号：AT01913848

申请日：2001-03-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LACHNER RUDOLF ,  SCHWERD MARKUS ,  SCHRENK MICHAEL

IPC: H01G4/33 ,  H01L29/92 ,  H01L21/02 ,  H01L23/522

Abstract: The integrated component has a number of conductor paths (13) and a capacitor (12) with a dielectric layer (5) between 2 electrode layers (14,15), which together are provided using the same sequence of metallisation layers (3,4,7-11) as that for the adjacent conductor path. The capacitor electrode layers may each be coupled to an underlying or overlying metal conductor path layer via a perpendicular connection (2,16), e.g. formed in an underlying intermediate dielectric layer (1).

公开(公告)号：DE102005047111B3

公开(公告)日：2007-06-21

申请号：DE102005047111

申请日：2005-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STICH ANDREAS ,  SCHRENK MICHAEL ,  SCHINDLER GUENTHER ,  ENGELHARDT MANFRED

IPC: H01L27/08 ,  H01L21/768 ,  H01L21/822

Abstract: Capacitor has a capacitor electrode (E1) formed on a surface of an intermediate dielectric (1). Another intermediate dielectric (4) is formed on the intermediate dielectric (1) and includes an opening for exposing a part of the capacitor electrode. An electrically conductive diffusion-barrier layer (5) is formed on the surface of the capacitor electrode. Another capacitor electrode (E2) is formed on a surface of a capacitor dielectric (6) and includes only another electrically conductive diffusion-barrier layer (7). One of the capacitor electrodes includes titanium, tantalum, tantalum nitride and/or titanium nitride. An independent claim is also included for a method of manufacturing a metal-insulator-metal capacitor.

公开(公告)号：AU2002358618A1

公开(公告)日：2003-07-09

申请号：AU2002358618

申请日：2002-12-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHRENK MICHAEL ,  KOLLER KLAUS ,  KORNER HEINRICH

IPC: H01L21/02 ,  H01L21/768 ,  H01G4/12 ,  H01G4/08 ,  H01L29/92

Abstract: To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric auxiliary layer ( 6 ) is deposited on a first electrode ( 2, 3, 5 ). This auxiliary layer ( 6 ) is then opened up ( 15 ) via the first electrode. Then, a dielectric layer ( 7 ) is produced, and the metal track stack ( 8, 9, 10 ) for the second electrode is then applied to the dielectric layer ( 6 ). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.

公开(公告)号：DE502006006768D1

公开(公告)日：2010-06-02

申请号：DE502006006768

申请日：2006-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENGELHARDT MANFRED ,  STICH ANDREAS ,  SCHINDLER GUENTHER ,  SCHRENK MICHAEL

IPC: H01G4/33 ,  H01G4/40 ,  H01L21/02 ,  H01L27/13

Abstract: Capacitor has a capacitor electrode (E1) formed on a surface of an intermediate dielectric (1). Another intermediate dielectric (4) is formed on the intermediate dielectric (1) and includes an opening for exposing a part of the capacitor electrode. An electrically conductive diffusion-barrier layer (5) is formed on the surface of the capacitor electrode. Another capacitor electrode (E2) is formed on a surface of a capacitor dielectric (6) and includes only another electrically conductive diffusion-barrier layer (7). One of the capacitor electrodes includes titanium, tantalum, tantalum nitride and/or titanium nitride. An independent claim is also included for a method of manufacturing a metal-insulator-metal capacitor.

公开(公告)号：DE102007019811A1

公开(公告)日：2008-11-06

申请号：DE102007019811

申请日：2007-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GLAS ALEXANDER ,  HARTUNG WOLFGANG ,  SCHRENK MICHAEL ,  KLEIN WOLFGANG ,  KEBINGER HERBERT

IPC: H01L27/06 ,  H01L23/488 ,  H01L23/60 ,  H03H7/01

Abstract: The circuit (100) has a contact (110) for electrically attaching a circuit, and a coil, which is arranged around the contact. An inner lying coil connection (122) of the coil (120) is arranged, and is electrically coupled with the contact. A circuit element is provided, where the coil is arranged around the circuit element, and a connection of the circuit element is electrically coupled with the contact. The connection forms the contact of the circuit element. An independent claim is also included for a chip integrated filter circuit.