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    1.
    发明专利
    未知

    公开(公告)号：DE10334387A1

    公开(公告)日：2004-04-15

    申请号：DE10334387

    申请日：2003-07-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ALEXANDER GEORGE WILLIAM ,  BAKER STEVEN M ,  HUCKABY JENNIFER FAYE ,  MA DAVID SUITWAI

    IPC: G11C7/10 ,  G11C7/16 ,  G11C11/4096 ,  G11C11/4193 ,  G11C29/02 ,  G11C5/14

    Abstract: A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplexing circuit, the analog-to-digital converter sequentially connects to each voltage source and converts the measured voltage level of the source to a binary word. The interface circuit presents the binary word, e.g., serially, to test equipment off the integrated circuit.

    5.
    发明专利
    未知

    公开(公告)号：DE10321441A1

    公开(公告)日：2003-12-04

    申请号：DE10321441

    申请日：2003-05-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOSCH CATHERINE ,  HUCKABY JENNIFER FAYE ,  NINO JR LEONEL R ,  PARTSCH TORSTEN

    IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4076

    Abstract: A circuit and method of operation for combining commands in a DRAM (dynamic random access memory) are revealed. The method applies to DRAMs having a plurality of memory banks or arrays. The method combines commands to rows on different memory banks, and the method also combines row and column commands on different memory banks. The method eliminates steps in a sequence of commands, and may significantly increase speed of input/output to a DRAM.

    7.
    发明专利
    未知

    公开(公告)号：DE10330111A1

    公开(公告)日：2004-04-08

    申请号：DE10330111

    申请日：2003-07-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOSCH KATHERINE ,  EDMONDS JOHNATHAN ,  HUCKABY JENNIFER FAYE ,  NINO JUN LEONEL R ,  PARTSCH TORSTEN

    IPC: G11C11/4072 ,  G11C29/00

    Abstract: A method of self-repair for a DRAM integrated circuit includes internally generating a bit pattern and writing the pattern to an array of memory cells within the integrated circuit. The DRAM integrated circuit reads from the array and internally compares the read data with the generated pattern to determine addresses for failed memory cells. The DRAM integrated circuit sets internal soft fuses that record the addresses of the failed memory cells and provide substitute memory cells for the failed memory cells from a redundant memory portion of the array. The self-repair process occurs each time the DRAM integrated circuit is powered up, thus permitting the integrated circuit to adapt to failures when installed in electronic devices and lessening the need for repair during manufacturing.

    8.
    发明专利
    未知

    公开(公告)号：DE10334386A1

    公开(公告)日：2004-02-26

    申请号：DE10334386

    申请日：2003-07-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： EDMONDS JOHNATHAN ,  HUCKABY JENNIFER FAYE ,  PARTSCH TORSTEN

    IPC: G01K7/42 ,  G05B19/042 ,  H01L23/58 ,  G06F1/04

    Abstract: A method of throttling the frequency with which an integrated circuit is accessed includes sensing the temperature of the integrated circuit die and converting the sensed temperature to a digital signal. The digital signal is stored in a register of the integrated circuit. The digital signal is read, and the frequency with which the integrated circuit is accessed is adjusted dependent at least in part upon the temperature of the die as indicated by the digital signal.

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