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    RANDOM ACCESS MEMORY WITH POST-AMBLE DATA STROBE SIGNAL NOISE REJECTION
    1.
    发明申请
    RANDOM ACCESS MEMORY WITH POST-AMBLE DATA STROBE SIGNAL NOISE REJECTION 审中-公开
    带有后置数据的随机存取存储器信号噪声抑制

    公开(公告)号：WO2005031746A3

    公开(公告)日：2005-06-23

    申请号：PCT/EP2004010747

    申请日：2004-09-24

    Applicant: INFINEON TECHNOLOGIES AG ,  ALEXANDER GEORGE WILLIAM ,  HAN JONGHEE ,  PARTSCH TORSTEN

    Inventor： ALEXANDER GEORGE WILLIAM ,  HAN JONGHEE ,  PARTSCH TORSTEN

    IPC: G11C7/10

    CPC classification number: G11C7/1078 ,  G11C7/1087 ,  G11C7/1093

    Abstract: A random access memory comprises a first circuit (130) configured to receive a strobe signal (132) and provide pulses in response to transitions in the strobe signal. The random access memory comprises a second circuit (100, 100n) configured to receive the strobe signal to latch data into the second circuit, and to receive the pulses to latch the latched data into the second circuit after the transitions in the strobe signal.

    Abstract translation: 随机存取存储器包括被配置为接收选通信号（132）并响应于选通信号中的转变提供脉冲的第一电路（130）。 随机存取存储器包括被配置为接收选通信号以将数据锁存到第二电路中的第二电路（100,100n），并且在选通信号中的转换之后接收脉冲以将锁存的数据锁存到第二电路中。

    6.
    发明专利
    未知

    公开(公告)号：DE112004001676T5

    公开(公告)日：2006-07-20

    申请号：DE112004001676

    申请日：2004-09-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ALEXANDER GEORGE WILLIAM ,  HAN JONGHEE ,  PARTSCH TORSTEN

    IPC: G11C7/10

    Abstract: A random access memory includes a control circuit configured to receive a strobe signal and generate a pulse after one edge of the strobe signal and before the next edge of the strobe signal for each cycle of a clock signal and a latch circuit configured to receive the strobe signal and the pulse. The latch circuit is configured to latch data signals into the latch circuit with the strobe signal and to receive the pulse to prevent post-amble noise on the strobe signal from latching other signals into the latch circuit.

    7.
    发明专利
    未知

    公开(公告)号：DE10334387A1

    公开(公告)日：2004-04-15

    申请号：DE10334387

    申请日：2003-07-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ALEXANDER GEORGE WILLIAM ,  BAKER STEVEN M ,  HUCKABY JENNIFER FAYE ,  MA DAVID SUITWAI

    IPC: G11C7/10 ,  G11C7/16 ,  G11C11/4096 ,  G11C11/4193 ,  G11C29/02 ,  G11C5/14

    Abstract: A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplexing circuit, the analog-to-digital converter sequentially connects to each voltage source and converts the measured voltage level of the source to a binary word. The interface circuit presents the binary word, e.g., serially, to test equipment off the integrated circuit.

    10.
    发明专利
    未知

    公开(公告)号：DE102005059806A1

    公开(公告)日：2006-06-29

    申请号：DE102005059806

    申请日：2005-12-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ALEXANDER GEORGE WILLIAM ,  LE THOAI-THAI

    IPC: H03K19/003

    Abstract: An off-chip driver (OCD) circuit and technique to reduce skew between rising and falling edges of output signals as process conditions vary are provided. Variations in process conditions may result in stronger or weaker relative current drive between NMOS and PMOS transistors. One or more process-dependent compensating current paths may be added to conventional pull-up and/or pull-down current paths to compensate for process variations by supplementing the current drive of transistors used to charge (PMOS) or discharge (NMOS) an output node of and end driver (e.g., inverter) stage of an OCD.

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