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    CHIPCARD ARRANGEMENT
    1.
    发明申请
    CHIPCARD ARRANGEMENT 审中-公开
    SMART CARD ASSEMBLY

    公开(公告)号：WO0152184A3

    公开(公告)日：2002-02-07

    申请号：PCT/DE0004634

    申请日：2000-12-27

    Applicant: INFINEON TECHNOLOGIES AG ,  KUX ANDREAS

    Inventor： KUX ANDREAS

    IPC: G06K19/00 ,  G06K19/073 ,  G06K19/077 ,  H01L25/065

    CPC classification number: G06K19/072 ,  G06K19/07372 ,  G06K19/077 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention relates to a chipcard arrangement with a card-like support, in which a recess is provided, with at least two superimposed semiconductor chips (4, 5) arranged therein. Said chips exchange electrical signals and/or energy, with each other, by means of electrically conducting connectors, whereby the at least two semiconductor chips (4, 5) together have a minimum size of from 20 to 25 mm and the electrically conducting connection is achieved by means of a three-dimensional wiring in the semiconductor chip.

    Abstract translation: 与卡形载体的芯片卡装置，其中被设置的凹部，被布置在至少两个叠置的半导体芯片（4,5），其经由导电连接的电信号和/或能量，彼此交换，其中所述至少两个半导体芯片（4,5 ）一起具有20〜25毫米的最小尺寸和导电连接是通过在半导体芯片的三维布线来实现。

    SEMI-CONDUCTOR COMPONENT AS A DELAYING DEVICE AND USE THEREOF.
    2.
    发明申请
    SEMI-CONDUCTOR COMPONENT AS A DELAYING DEVICE AND USE THEREOF. 审中-公开
    半导体部件时延元件及半导体元件的使用

    公开(公告)号：WO0117025A2

    公开(公告)日：2001-03-08

    申请号：PCT/DE0003002

    申请日：2000-09-01

    Applicant: INFINEON TECHNOLOGIES AG ,  BRUECKLMEIER ERIC ROGER ,  PALM HERBERT ,  KUX ANDREAS

    Inventor： BRUECKLMEIER ERIC-ROGER ,  PALM HERBERT ,  KUX ANDREAS

    IPC: H01L29/423 ,  H01L29/788 ,  H01L29/00

    CPC classification number: H01L29/7883 ,  H01L29/42328

    Abstract: A floating gate cell is used as a clock whereby the charging process is delayed by the application of a sufficiently low charging voltage until a predetermined threshold voltage is reached. A particularly thin tunnel oxide layer can be provided in order to bring about a gradual discharge of a charged cell. Preferably, the floating gate electrode (5)is connected to the control gate electrode (16) of a second cell, which then delays the charging of the floating gate electrode (15) of the second cell.

    Abstract translation: 通过在充电过程的时间尺度被延迟，直到通过施加足够低的充电电压的预定阈值电压被使用的浮动栅极单元。 特别薄的隧道可旨在实现加载细胞的逐渐放电。 优选地，浮置栅极电极（5）到所述控制栅电极（16）连接到第二小区，其然后相应地降低时，浮置栅电极（15）加载所述第二小区。

    CIRCUIT
    3.
    发明申请
    CIRCUIT 审中-公开
    电路

    公开(公告)号：WO02054492A3

    公开(公告)日：2003-02-13

    申请号：PCT/DE0104589

    申请日：2001-12-06

    Applicant: INFINEON TECHNOLOGIES AG ,  KUX ANDREAS

    Inventor： KUX ANDREAS

    IPC: H01L23/544 ,  H01L23/58 ,  H01L29/06

    CPC classification number: H01L23/57 ,  H01L23/544 ,  H01L24/31 ,  H01L29/0657 ,  H01L2223/54473 ,  H01L2924/01068 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/19041

    Abstract: The invention relates to a circuit comprising a first substrate (1) which has an integrated circuit (4) in a first surface (3) and a second surface (2) opposite the same, and a second substrate (9) which has a sensor (7) on one surface. Said second substrate (9) is adhesively connected to the first substrate (1) in such a way that the surface of the second substrate (9) comprising the sensor (7) faces one of the two surfaces (2, 3) of the first substrate (1). It can thus be determined whether the arrangement consisting of the first and second substrate is divided or has been divided.

    Abstract translation: 具有第一衬底的电路布置（1），在第一表面（3）的集成电路（4）和相对的第二面（2）和MT的第二基板（9），使得传感器的表面（7）上 ，其中所述第二衬底（9）连接到第一基板（1）是这样附着第二基板的表面（9），其具有传感器（7），所述两个表面中的一个（2,3）的第一的 基板（1）面对。 因此，被检测的第一和第二衬底的排列是否被分离，或者在。

    Vertical structure integrated circuit arrangement
    10.
    发明专利
    Vertical structure integrated circuit arrangement 未知

    公开(公告)号：DE19957120A1

    公开(公告)日：2001-05-31

    申请号：DE19957120

    申请日：1999-11-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KUX ANDREAS ,  SMOLA MICHAEL

    IPC: G06K19/073 ,  G11C5/02 ,  H01L25/065

    Abstract: A vertical integrated circuit has at least two integrated part-circuits (1,2) arranged lying over one another, and which are interconnected so that on each of the part-circuits (1,2) is formed a digital memory device (4,6) and that a stored byte is split up into given bit-groups and, in each case, one bit-group of a byte is stored in each digital memory device (4,5) of the integrated part-circuit (1,2). At least one data-line (5) runs from the upper integrated part- circuit (1) through the latter to the lower integrated part- circuit (2), and the digital memory devices (4,6) of the different integrated part-circuits (1,2), are arranged directly lying over one another.

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