中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

24 records (took 0.022 seconds)

    SEMICONDUCTOR DEVICE WITH A MULTIPLE DIELECTRIC
    1.
    发明申请
    SEMICONDUCTOR DEVICE WITH A MULTIPLE DIELECTRIC 审中-公开
    与MEHRFACHDIELEKTRIKUM半导体器件

    公开(公告)号：WO0045441A3

    公开(公告)日：2001-03-29

    申请号：PCT/DE0000203

    申请日：2000-01-25

    Applicant: INFINEON TECHNOLOGIES AG ,  BACHHOFER HARALD ,  REISINGER HANS ,  HANEDER THOMAS PETER

    Inventor： BACHHOFER HARALD ,  REISINGER HANS ,  HANEDER THOMAS PETER

    IPC: H01L29/51 ,  H01L21/28

    CPC classification number: H01L29/511

    Abstract: The invention relates to a semiconductor device with a multiple dielectric, especially an ONO-triple dielectric, comprising a semiconductor substrate (10) of a first conduction type, a first doping area (20) of a second conduction type which is provided in said semiconductor substrate (10), a second doping area (30) of the second conduction type which is provided in the semiconductor substrate (10), a channel area (25) which is situated between the first and the second doping area (20, 30), a gate dielectric (40, 50, 60) which lies on top of the channel area (25) and which has at least three layers; and a gate terminal (70) which is provided on top of the gate dielectric (40, 50, 60). The bottom layer (40) of the gate dielectric (40, 50, 60) has an essentially smaller dielectric constant than the top layer (60) of the gate dielectric (40, 50, 60).

    Abstract translation: 本发明提供了一种具有Mehrfachdielektrikum的半导体器件，特别是ONO Dreifachdielektrikum，包括：第一导电类型的半导体衬底（10）; 一个在设置于第二导电型的第一杂质区（20）的半导体衬底（10）; 一个在设置于第二导电型的第二杂质区（30）的半导体衬底（10）; 一个所述第一和第二杂质区之间躺在（20，30）沟道区（25）; 一个在所述沟道区（25）下面的栅极电介质（40，50，60），其具有至少三个层; 及以上的栅极端子（70）设置在栅极电介质（40，50，60）。 栅极电介质（40，50，60）的底部层（40）的介电常数比所述栅极电介质（40，50，60）的最上层（60）显着更小。

    CAPACITOR ELECTRODE
    2.
    发明申请
    CAPACITOR ELECTRODE 审中-公开
    电容电极

    公开(公告)号：WO0036636A3

    公开(公告)日：2000-08-10

    申请号：PCT/DE9903926

    申请日：1999-12-08

    Applicant: INFINEON TECHNOLOGIES AG ,  WENDT HERMANN ,  BEITEL GERHARD ,  REISINGER HANS

    Inventor： WENDT HERMANN ,  BEITEL GERHARD ,  REISINGER HANS

    IPC: H01L21/02 ,  H01L21/285 ,  H01L21/8242

    CPC classification number: H01L28/75 ,  H01L28/55 ,  H01L28/60

    Abstract: The aim of the invention is to create a microelectronic structure which prevents oxidation of oxygen-sensitive structures (25). To this end, the microelectronic structure is provided with a conductive layer (10) consisting of a platinum iridium alloy. The iridium should hamper the oxygen diffusion through the conductive layer (10) by binding the oxygen when the microelectronic structure is treated in a oxygen-containing atmosphere. Oxidation-sensitive structures (25) are thus protected underneath the conductive layer (10).

    Abstract translation: 它是要创建的微电子结构，其防止对氧敏感的结构（25）的氧化。 为了这个目的，在微电子结构的导电层（10）由铂铱合金制成。 铱应通过结合氧气阻碍通过导电层（10）中的氧扩散，从而保护用一种处理微电子结构的导电层（10）下方的氧化敏感的结构（25）在含氧气氛。

    3.
    发明专利
    未知

    公开(公告)号：DE19947117B4

    公开(公告)日：2007-03-08

    申请号：DE19947117

    申请日：1999-09-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STENGL REINHARD ,  REISINGER HANS ,  HANEDER THOMAS ,  BACHHOFER HARALD

    IPC: H01L21/8247 ,  H01L29/78 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

    Abstract: A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

    10.
    发明专利
    未知

    公开(公告)号：DE59705303D1

    公开(公告)日：2001-12-13

    申请号：DE59705303

    申请日：1997-07-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHAEFER HERBERT ,  FRANOSCH MARTIN ,  STENGL REINHARD ,  LEHMANN VOLKER ,  REISINGER HANS ,  WENDT HERMANN

    IPC: H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3205

    Abstract: PCT No. PCT/DE97/01408 Sec. 371 Date Feb. 9, 1999 Sec. 102(e) Date Feb. 9, 1999 PCT Filed Jul. 3, 1997 PCT Pub. No. WO98/07184 PCT Pub. Date Feb. 19, 1998For manufacturing a capacitor that is essentially suited for DRAM arrangements, column structures that form an electrode of the capacitor are etched upon employment of a statistical mask that is produced without lithographic steps by nucleus formation of Si/Ge and subsequent selective epitaxy. Structure sizes below 100 nm can be realized in the statistical mask. Surface enlargement factors up to 60 are thus achieved.

Patent Agency Ranking