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    METHOD FOR PRODUCING A MEMORY CELL
    1.
    发明申请
    METHOD FOR PRODUCING A MEMORY CELL 审中-公开
    METHOD FOR CELL

    公开(公告)号：WO03067639A3

    公开(公告)日：2003-10-16

    申请号：PCT/DE0300183

    申请日：2003-01-23

    Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN HANNES

    Inventor： HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN HANNES

    IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

    Abstract: The invention relates to NROM memory cells that are disposed in trenches that are etched into the semiconductor material. The memory layer composed of a nitride layer (3) that is interposed between two oxide layers (2, 4) is applied to the trench walls before the dopants for source and drain (7) are implanted. The implantation regions of source and drain are thus prevented from being damaged by the high temperature loads of the component during production of the memory layer as the respective dopant is introduced only later on. Polysilicon gate electrodes (5) are connected to word lines (11).

    Abstract translation: 的NROM存储单元被布置在被蚀刻到半导体材料中的沟槽。 氧化物层之间的氮化物层（3）的存储层（2,4）的掺杂剂为源极和漏极（7）到被植入之前施加到坟墓壁。 以这种方式，实现了在所述存储层的制造部件的高温负荷不能与源和漏区的注入干扰，如在讨论的掺杂剂将只随后引入。 由多晶硅制成的栅电极（5）被连接到字线（11）。

    2.
    发明专利
    未知

    公开(公告)号：DE10204873C1

    公开(公告)日：2003-10-09

    申请号：DE10204873

    申请日：2002-02-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOFMANN FRANZ ,  LUYKEN HANNES ,  LANDGRAF ERHARD

    IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8239

    Abstract: Method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor layer structure above a channel region provided between doped source-drain regions. The method includes the steps of fabricating at least one trench in the top side, providing at least portions of the trench walls which adjoin the source-drain regions to be fabricated with the storage layer, depositing a material provided for the gate electrode into the trench, forming the source-drain regions by covering the gate electrode, removing, on both sides of the trench, the semiconductor material down to an intended depth, and implanting dopant, and applying an insulation layer to the source-drain region, and fabricating an electrical connection for the gate electrode.

    3.
    发明专利
    未知

    公开(公告)号：DE102005047058A1

    公开(公告)日：2007-04-12

    申请号：DE102005047058

    申请日：2005-09-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHLOESSER TILL ,  WEIS ROLF ,  MOLL HANS-PETER ,  POPP MARTIN ,  STRASSER MARC ,  LUYKEN HANNES

    IPC: H01L21/336 ,  H01L29/78

    Abstract: In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

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