公开(公告)号：DE19816446B4

公开(公告)日：2005-11-17

申请号：DE19816446

申请日：1998-04-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BLOCH MARTIN ,  GEORGAKOS GEORG ,  KASPRICK KAI ,  KERN THOMAS ,  PETER JUERGEN ,  PIOREK THOMAS

IPC: G11C16/12 ,  H03K3/356 ,  H03K17/10

公开(公告)号：DE10217870A1

公开(公告)日：2003-11-13

申请号：DE10217870

申请日：2002-04-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEDER UWE ,  DAAK MATTHIAS VON ,  PIOREK THOMAS

IPC: G11C7/06 ,  G11C7/12 ,  G11C16/26

公开(公告)号：DE102005024648A1

公开(公告)日：2006-11-30

申请号：DE102005024648

申请日：2005-05-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SATTLER SEBASTIAN ,  MATTES HEINZ ,  STROEBLE OLAF ,  PIOREK THOMAS

IPC: G04F10/00 ,  G01R31/317

Abstract: An electrical circuit used for measuring times is disclosed. In one embodiment, the electrical circuit has a counter, a decoder and a multiplicity of time trap elements. At least the counter and the time trap elements are located together on an integrated semiconductor component. Each time trap element has a data input, a clock input, a delay output and a output port. The time trap element contains a delay element and a flip flop. The delay element outputs a signal change at the data input with a time delay at the delay output. The flip flop has a data input, a clock input and an output port, the data inputs, the clock inputs and the output ports of the flip flop and of the time trap element being connected to one another. The time trap elements are connected as ring oscillator.

公开(公告)号：DE59913841D1

公开(公告)日：2006-10-26

申请号：DE59913841

申请日：1999-01-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GEORGAKOS GEORG ,  KASPRICK KAI ,  PETER JUERGEN ,  BLOCH MARTIN ,  KERN THOMAS DR ,  PIOREK THOMAS

IPC: G11C16/02 ,  G11C16/06 ,  G11C16/04 ,  G11C16/10

Abstract: The EEPROM has several memory cells which can be programmed, read out from and erased via selection, control, bit and source lines. The memory cells each have a memory transistor and a selection transistor connected in series with the memory transistor. The drain terminal of the memory transistor is connected to the bit line. The source terminal of the selection transistor is connected to the source line. A control unit is provided. This is arranged such that the programming voltage required for programming a memory cell is fed via the source line. Separate source lines may be provided for individual memory cells of groups of memory cells. The source lines are preferably adapted to apply high voltages to the memory cells.

公开(公告)号：DE10217870B4

公开(公告)日：2004-02-26

申请号：DE10217870

申请日：2002-04-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEDER UWE ,  DAAK MATTHIAS VON ,  PIOREK THOMAS

IPC: G11C7/06 ,  G11C7/12 ,  G11C16/26

公开(公告)号：DE10015276A1

公开(公告)日：2001-10-11

申请号：DE10015276

申请日：2000-03-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VERBECK MICHAEL ,  PIOREK THOMAS

IPC: G05F3/26 ,  G05F1/10 ,  G11C5/14

Abstract: The invention relates to a current generating device characterized in that it is designed for, in response to predetermined events, temporarily impressing a current, which is modified in comparison to the usual current, onto the device connected to the current generating device. In addition, the voltage generating device is designed for, in response to predetermined events, temporarily applying a voltage, which is modified in comparison to the usual voltage, to the device connected to the voltage generating device.