公开(公告)号：DE50109266D1

公开(公告)日：2006-05-11

申请号：DE50109266

申请日：2001-09-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG DR ,  LAMMERS STEFAN ,  GOGL DR ,  ROEHR DR

IPC: G11C11/14 ,  G11C11/16 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: The arrangement has memory cells in a field in at least one plane at intersection points between word or programming lines and bit lines. Providing programming currents to word and bit lines corresponding to a selected cell causes stray magnetic fields in adjacent cells. The method involves feeding a compensation current to the adjacent cell word, programming, bit or special line to produce a compensation magnetic field countering the stray field. The MRAM arrangement has memory cells (11-13) in a memory cell field in at least one plane at intersection points between word lines (WL1) or programming lines and bit lines (BL1-BL3). Providing programming currents to word and bit lines corresponding to a selected cell causes stray magnetic fields in adjacent cells. The method involves feeding a compensation current to the word line or programming line or bit line or a special line of the adjacent cell(s) to produce a compensation magnetic field countering the stray field.

公开(公告)号：DE59910447D1

公开(公告)日：2004-10-14

申请号：DE59910447

申请日：1999-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  BRAUN GEORG ,  MANYOKI ZOLTAN ,  ROEHR DR ,  BOEHM THOMAS

IPC: G11C8/00 ,  G11C8/10 ,  H03K19/084 ,  H03K19/094 ,  H03K19/23 ,  H03M5/16

Abstract: An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential.