公开(公告)号：WO02073657A3

公开(公告)日：2003-05-22

申请号：PCT/DE0200788

申请日：2002-03-05

Applicant: INFINEON TECHNOLOGIES AG ,  GUSTIN WOLFGANG ,  GRUENING VON SCHWERIN ULRIKE ,  TEMMLER DIETMAR ,  SCHREMS MARTIN ,  RONGEN STEFAN ,  STRASSER RUDOLF

Inventor： GUSTIN WOLFGANG ,  GRUENING VON SCHWERIN ULRIKE ,  TEMMLER DIETMAR ,  SCHREMS MARTIN ,  RONGEN STEFAN ,  STRASSER RUDOLF

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10867 ,  H01L27/10873

Abstract: According to the invention, a trench capacitor is formed inside a trench (30) that is arranged inside a substrate (20). The trench (30) is filled with a conductive trench filling (50) that serves as an inner capacitor electrode. An epitaxial layer (75) is grown on the lateral wall of the trench (30) on the substrate (20). A buried contact (60) is arranged between the conductive trench filling (50) with the second intermediate layer (65) and the epitaxially grown layer (75). A dopant out-diffusion (80), which is formed while leading out from the buried contact (60), is arranged inside the epitaxially grown layer (75). The epitaxially grown layer (75) enables the dopant out-diffusion (80) to be further removed from a selection transistor (10) located next to the trench whereby permitting the prevention of short channel effects in the selection transistor (10).

Abstract translation: 它是在一个沟槽30，其被布置在基底20的严重电容器形成 沟槽30填充有导电填充严重50作为内部电容器电极。 在沟槽30的基板20上的侧壁，外延层75生长。 导电填充坟50与第二中间层65和外延生长层75，掩埋接触60布置之间。 在一个Dotierstoffausdiffusion 80被布置在外延生长层75，这是从所述掩埋接触60出来而形成。 通过外延生长层75，Dotierstoffausdiffusion 80进一步远离相邻排列的选择晶体管10，从而短沟道效应可以在选择晶体管10度可以避免沟槽。

公开(公告)号：DE10146888C1

公开(公告)日：2003-04-10

申请号：DE10146888

申请日：2001-09-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUETZEN JOERN ,  RONGEN STEFAN ,  SCHMIDT BARBARA ,  SCHREMS MARTIN ,  KOEHLER DANIEL

IPC: C09K13/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/461 ,  H01L21/8242

Abstract: To fabricate a trench capacitor in a substrate, a trench is formed in the substrate. The trench has an upper region and a lower region. In the trench, first of all nanocrystallites and/or a seed layer for nanocrystallites are deposited in the upper region and the lower region. Then, the nanocrystallites and/or the seed layer are removed from the upper region of the trench by means of an etching process. The etching parameters of the etching process are selected in such a way that the seed layer and/or the nanocrystallites which are uncovered in the upper region and the lower region are removed only from the upper region. Consequently, an expensive mask layer can be avoided in the lower region of the trench.

公开(公告)号：DE102005044142B3

公开(公告)日：2007-03-01

申请号：DE102005044142

申请日：2005-09-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RONGEN STEFAN ,  WURSTER KAI ,  ORTH ANDREAS ,  HAUPT MORITZ

IPC: H01L21/822 ,  H01L27/08

Abstract: A production process for an electrically conductive filling (30) in a trench in a semiconductor substrate (10) or layer comprises preparing the substrate and trench, depositing amorphous or polycrystalline silicon and phosphorus simultaneously in the trench and then forming at least one monolayer of arsenic atoms on the silicon/phosphorus interface. An independent claim is also included for a trench capacitor in a semiconductor substrate as above.