中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4 records (took 0.027 seconds)

    METHOD FOR PRODUCTION OF A SEMICONDUCTOR STRUCTURE
    1.
    发明申请
    METHOD FOR PRODUCTION OF A SEMICONDUCTOR STRUCTURE 审中-公开
    制造半导体结构的方法

    公开(公告)号：WO2004025714A3

    公开(公告)日：2004-05-13

    申请号：PCT/EP0309551

    申请日：2003-08-28

    Applicant: INFINEON TECHNOLOGIES AG ,  GENZ OLIVER ,  KIRCHHOFF MARKUS ,  MACHILL STEFAN ,  REB ALEXANDER ,  SCHMIDT BARBARA ,  STAVREV MOMTCHIL ,  STEGEMANN MAIK ,  WEGE STEPHAN

    Inventor： GENZ OLIVER ,  KIRCHHOFF MARKUS ,  MACHILL STEFAN ,  REB ALEXANDER ,  SCHMIDT BARBARA ,  STAVREV MOMTCHIL ,  STEGEMANN MAIK ,  WEGE STEPHAN

    IPC: H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8244

    CPC classification number: H01L21/76811 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31144

    Abstract: The invention relates to a method for production of a semiconductor structure, comprising the steps: preparation of a semiconductor substrate (1), generation of a lower first, a middle second and an upper third masking layer (5, 7, 9) on a surface of the semiconductor substrate (1), formation of at least one first window (11, 11a-h) in the upper third masking layer (9), structuring the middle second masking layer (7) using the first window (11, 11a-h) in the upper third masking layer (9) for the transfer of the first window (11, 11a-h), structuring the lower first masking layer (5) using the first window (11, 11a-h) in the middle second masking layer (7) for the transfer of the first window (11, 11a-h), enlarging the first window (11, 11a-h) in the upper third masking layer (9) to form a second window (13, 13a-b) in a maskless process step, restructuring the middle second masking layer (7) using the second window (13, 13a-b) in the upper third masking layer (9) for the transfer of the second window (13, 13a-b), structuring the semiconductor substrate (1), using the structured lower third masking layer (5), restructuring the lower first masking layer (5) using the second window (13, 13a-b) in the middle second masking layer (7) and restructuring the semiconductor substrate (1) using the restructured lower third masking layer (5).

    Abstract translation: 本发明提供了一种半导体结构制造方法，包括以下步骤：提供半导体衬底（1）; 在所述半导体衬底（1）的表面上提供下第一掩膜层，中间第二掩膜层和上第三掩膜层（5,7,9）; 在所述上部第三掩模层（9）中形成至少第一窗口（11,11a-h）; 使用上部第三掩模层（9）中的第一窗口（11,11a-h）图案化中间第二掩模层（7）以传递第一窗口（11,11a-h）; 使用中间第二掩模层（7）中的第一窗口（11,11a-h）构造下部第一掩模层（5）以传送第一窗口（11,11a-h）; 扩大上部第三掩模层（9）中的第一窗口（11,11a-h）以在无掩模工艺步骤中形成第二窗口（13,13a-b）; 使用上部第三掩模层（9）中的第二窗口（13,13a-b）重构中央第二掩模层（7）以传送第二窗口（13,13a-b）; 使用图案化的下第三掩模层（5）图案化半导体衬底（1）; 使用中间第二掩模层（7）中的第二窗口（13,13a-b）重构下部第一掩模层（5）; 以及使用重构的下第三掩模层（5）重构半导体衬底（1）。

    2.
    发明专利
    未知

    公开(公告)号：DE10146888C1

    公开(公告)日：2003-04-10

    申请号：DE10146888

    申请日：2001-09-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LUETZEN JOERN ,  RONGEN STEFAN ,  SCHMIDT BARBARA ,  SCHREMS MARTIN ,  KOEHLER DANIEL

    IPC: C09K13/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/461 ,  H01L21/8242

    Abstract: To fabricate a trench capacitor in a substrate, a trench is formed in the substrate. The trench has an upper region and a lower region. In the trench, first of all nanocrystallites and/or a seed layer for nanocrystallites are deposited in the upper region and the lower region. Then, the nanocrystallites and/or the seed layer are removed from the upper region of the trench by means of an etching process. The etching parameters of the etching process are selected in such a way that the seed layer and/or the nanocrystallites which are uncovered in the upper region and the lower region are removed only from the upper region. Consequently, an expensive mask layer can be avoided in the lower region of the trench.

Patent Agency Ranking