公开(公告)号：JP2004297050A

公开(公告)日：2004-10-21

申请号：JP2004063836

申请日：2004-03-08

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： SCHINDLER GUENTHER

IPC: B81B3/00 ,  H01L21/822 ,  H01L27/04 ,  H02K35/02

CPC classification number: H02K35/02

Abstract: PROBLEM TO BE SOLVED: To provide a monolithic integrated circuit structure having a function unit suitable for remote operation, to which electric energy is autonomously supplied. SOLUTION: This monolithic integrated circuit structure has a substrate, a function unit formed in and/or on the substrate, and an energy supply unit which is formed in and/or on the substrate and is connected to the function unit. The energy supply unit has an inductance and a permanent magnet. The inductance and the permanent magnet are installed so that the permanent magnet can be moved in relation to the inductance by oscillations generated in the circuit structure, that is, so that an electric voltage for supplying electric energy to the function unit can be induced. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2011129939A

公开(公告)日：2011-06-30

申请号：JP2011009120

申请日：2011-01-19

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アーゲー

Inventor： GABRIC ZVONIMIR ,  PAMLER WERNER ,  SCHINDLER GUENTHER ,  STICH ANDREAS

IPC: H01L23/522 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/768

CPC classification number: H01L21/7682

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing an air gap between conductor tracks that decreases in coupling capacity and is improved in mechanical or electrical characteristics as compared with conventional examples. SOLUTION: A conductor track array includes bases 1 and 2, at least two conductor tracks 4, a cavity 6, and a resist layer 5 covering the conductor tracks 4 to close the cavity 6. A carrier track TB having a width B2 narrower than the width B1 of the conductor tracks 4 is formed to form the air gap for reducing coupling capacity and signal delay by self-alignment technique below the conductor tracks 4 along side faces thereof. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造传导轨道之间的空气间隙的方法，其与传统实例相比降低了耦合能力，并提高了机械或电气特性。 解决方案：导体轨道阵列包括基座1和2，至少两个导体轨道4，空腔6和覆盖导体轨道4以封闭空腔6的抗蚀剂层5.具有宽度B2的载体轨道TB 形成比导体轨道4的宽度B1窄的狭缝，以形成气隙，用于通过导电轨道4沿着其侧面的自对准技术降低耦合电容和信号延迟。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007088439A

公开(公告)日：2007-04-05

申请号：JP2006224010

申请日：2006-08-21

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： GABRIC ZVONIMIR ,  PAMLER WERNER ,  SCHINDLER GUENTHER ,  STICH ANDREAS

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/7682

Abstract: PROBLEM TO BE SOLVED: To provide a conductive track array with reduced coupling capacity and improved mechanical and electrical properties, and its manufacturing method. SOLUTION: The conductive track array includes substrates 1 and 2, at least two conductive tracks 4, cavity 6, and a resist layer 5 that fills up the cavity 6 and covers the conductive track 4. An air gap to reduce the coupling capacity and signal delay by forming a carrier track TB with width of B2, which is smaller than the width B1 of the conductive track 4, is formed under the conductive track 4 along its side wall using a self-align technology. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有降低的耦合能力和改善的机械和电气性能的导电轨道阵列及其制造方法。 解决方案：导电轨道阵列包括衬底1和2，至少两个导电轨道4，空腔6以及填充空腔6并覆盖导电轨道4的抗蚀剂层5。 使用自对准技术，通过形成宽度小于导电轨道4的宽度B1的B2的载体轨道TB，沿着其侧壁形成在导电轨道4的下方的容量和信号延迟。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2005071739A3

公开(公告)日：2006-03-02

申请号：PCT/DE2005000088

申请日：2005-01-22

Applicant: INFINEON TECHNOLOGIES AG ,  GABRIC ZVONIMIR ,  PAMLER WERNER ,  SCHINDLER GUENTHER

Inventor： GABRIC ZVONIMIR ,  PAMLER WERNER ,  SCHINDLER GUENTHER

IPC: C23C16/30 ,  H01L21/314 ,  H01L21/764 ,  H01L21/768 ,  C23C16/40 ,  H01L21/76

CPC classification number: H01L21/764 ,  C23C16/308 ,  H01L21/3145 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: The invention relates to a plasma-excited chemical vapor deposition method for forming a silicon/oxygen/nitrogen-containing material. The invention provides that during the supply of silicon material and oxygen material, nitrogen material is supplied while using an organic silicon precursor material.

Abstract translation: 本发明涉及等离子体增强化学气相沉积工艺用于形成含有硅 - 氧 - 氮的材料，其中，所述含氮材料由硅材料和氧材料的供应过程中使用有机硅前体材料提供。

公开(公告)号：WO0065658A3

公开(公告)日：2001-03-29

申请号：PCT/DE0001303

申请日：2000-04-20

Applicant: INFINEON TECHNOLOGIES AG ,  WEINRICH VOLKER ,  SCHINDLER GUENTHER ,  MAZURE ESPEJO CARLOS

Inventor： WEINRICH VOLKER ,  SCHINDLER GUENTHER ,  MAZURE-ESPEJO CARLOS

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/06 ,  H01L27/105 ,  H01L21/8242

CPC classification number: H01L28/60 ,  H01L21/32136 ,  H01L27/0688

Abstract: The invention relates to a method of producing a high-epsilon dielectric/ferroelectric capacitor. According to the inventive method, a structural layer (10) with a central base-layer zone (11) and a trench (13) that is filled with Si and that laterally surrounds said layer is produced. A metal layer (14) is deposited on said layer and is siliconized above the Si-filled trench (13). When the siliconized metal layer section (18) is oxidized, it migrates into the trench (13), thereby forming a base electrode (19) above the base-layer zone (11).

Abstract translation: 在用于与中央基体层区（11）和有Si填充的沟槽围绕该横向制造高电介质基-ε-/铁电电容器结构化层（10）的方法（13）被产生。 此外，金属层（14）沉积和硅化在Si填充的沟槽（13）。 通过在沟槽（13），其特征在于，形成具有基极电极（19）的基本层区（11）氧化硅化金属层部分（18）迁移到这一点。

公开(公告)号：WO02071483A3

公开(公告)日：2003-03-06

申请号：PCT/DE0200758

申请日：2002-03-01

Applicant: INFINEON TECHNOLOGIES AG ,  ENGELHARDT MANFRED ,  SCHINDLER GUENTHER

Inventor： ENGELHARDT MANFRED ,  SCHINDLER GUENTHER

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/53295 ,  H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A conductor track arrangement (100) comprises, on a first layer (101), a first layer surface (102) and at least two conductor tracks (104), which are arranged on the first layer surface and which have a second layer surface (105) that is essentially parallel to the first layer surface (102). A second layer (106) is arranged on the second layer surface of each conductor track (104), whereby the second layers (106) of adjacent conductor tracks overlap areas located between the adjacent conductor tracks (104). A third layer (107) is arranged on said second layer and completely occludes the areas located between the adjacent conductor tracks (104) by overlapping the same.

Abstract translation: 互连组件（100）包括在其上的至少两个导电迹线（104）具有基本上与第一层表面上的第一层（101），第一层表面（102）（102）平行的第二层表面（105）在其上，分别，第二层 （106）每一个导体轨道（104），其中，相邻的导体轨迹的第二层（106）重叠在相邻的导体轨（104）之间的区域，并在其上通过完全重叠的方式覆盖在相邻的导体轨（104）之间的区域的第三层（107） 总结。

公开(公告)号：WO02101820A2

公开(公告)日：2002-12-19

申请号：PCT/DE0201983

申请日：2002-05-29

Applicant: INFINEON TECHNOLOGIES AG ,  ENGELHARDT MANFRED ,  SCHINDLER GUENTHER

Inventor： ENGELHARDT MANFRED ,  SCHINDLER GUENTHER

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76885 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A conductor track arrangement (100) comprises a first layer (101) with an integrated conductor track (102), above which is a second layer (106), above which is a third layer (108) with an integrated conductor track (109), an electrical contact (104) in the second layer (106), coupling the conductor tracks (102, 109), whereby the conductor tracks (102, 109) and the electrical contact (104) comprise an electrically conducting material which are surrounded by an encapsulation layer (103, 107, 109) made from an encapsulation material which is mechanically harder than the electrically conducting material.

Abstract translation: 互连组件（100）包括具有集成导体线路（102）的第一层（101）上的第二层（106），约一第三层（108），具有集成导体轨道（109），一个导体路径（102， 109）耦合的电接触（104）（在第二层106），其中，所述导体轨迹（102，109）和所述电接触件（104）包括导电材料和（从胶囊材料的封装层103，107，109） 被封闭，其比导电材料机械地更硬。

公开(公告)号：WO0241339A3

公开(公告)日：2002-08-22

申请号：PCT/DE0104248

申请日：2001-11-13

Applicant: INFINEON TECHNOLOGIES AG ,  GABRIC ZVONIMIR ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  SCHINDLER GUENTHER

Inventor： GABRIC ZVONIMIR ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  SCHINDLER GUENTHER

IPC: H01L21/02 ,  H01L21/285 ,  H01L27/115 ,  H01L21/3205

CPC classification number: H01L27/11502 ,  H01L21/28568 ,  H01L28/55 ,  H01L28/75

Abstract: The invention relates to a method for producing a ferroelectric capacitor, especially in large-scale integrated, non-volatile semiconductor memories, and to an integrated ferroelectric semiconductor memory arrangement. In order to prevent damage to the ferro- or paraelectric (6), a TaSixNy barrier layer (7) is deposited over the capacitor module (1). The TaSixNy material has barrier properties in relation to hydrogen diffusion and Ti diffusion.

Abstract translation: 本发明涉及一种用于制造铁电电容器的方法，特别是在高度集成的非易失性半导体存储器和集成铁电半导体存储器件中。 为了避免损坏铁电或顺电（6），在电容器模块（1）上沉积TaSixNy阻挡层（7）。 TaSixNy材料具有对氢扩散和Ti扩散的阻隔性能。

公开(公告)号：WO02091432A3

公开(公告)日：2003-05-01

申请号：PCT/EP0204422

申请日：2002-04-22

Applicant: INFINEON TECHNOLOGIES AG ,  HARTNER WALTER ,  GABRIC ZVONIMIR ,  KROENKE MATTHIAS ,  SCHINDLER GUENTHER

Inventor： HARTNER WALTER ,  GABRIC ZVONIMIR ,  KROENKE MATTHIAS ,  SCHINDLER GUENTHER

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/00 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L28/55 ,  H01L23/564 ,  H01L27/11502 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a microelectronic structure, which provides improved protection of a hydrogen-sensitive dielectric against hydrogen contamination. According to the invention, the hydrogen-sensitive dielectric (14) is covered at least by an intermediate oxide (18), whose material thickness is at least five times the thickness of the hydrogen-sensitive dielectric. The intermediate oxide (18) simultaneously acts as an intermetal dielectric and is metallized on its surface for this purpose. The intermediate oxide (18), which has a sufficient thickness, absorbs the hydrogen that may be released during the deposition of a hydrogen barrier layer (22, 26), thus protecting the hydrogen-sensitive dielectric (14).

Abstract translation: 建议用之前的氢污染氢敏感电介质的改进的保护微电子结构。 为了这个目的，提供了氢气敏感电介质（14），以至少覆盖中间氧化物（18），其厚度为氢敏电介质的厚度的至少五倍。 中间氧化物（18）同时用作金属间介电，并且因此携带在其上侧金属化。 的足够厚的中间氧化物（18）吸收可能在氢阻挡层（22，26）释放的氢的沉积和保护氢敏感电介质（14）。

公开(公告)号：DE102005039323B4

公开(公告)日：2009-09-03

申请号：DE102005039323

申请日：2005-08-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GABRIC ZVONIMIR ,  STICH ANDREAS ,  PAMLER WERNER ,  SCHINDLER GUENTHER

IPC: H01L23/522 ,  H01L21/768

Abstract: A conduction path arrangement has a substrate (1,2), at least two conduction paths (4), formed adjacent to one another over the substrate, and a cavity which is formed at least between the conduction paths (4), and a dielectric covering layer (5) covering the conduction paths and enclosing the cavity. The support paths (TB) between the substrate (1,2) and the conduction paths (4) are designed to support the conduction paths, in which on the contact surface, a width (B1) of the conduction paths is greater than a width (B2) of the support paths (TB). An independent claim is included for a method for fabrication a conduction path arrangement.