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    Method of manufacturing conductor track array
    1.
    发明专利
    Method of manufacturing conductor track array 有权
    制造导线跟踪阵列的方法

    公开(公告)号：JP2011129939A

    公开(公告)日：2011-06-30

    申请号：JP2011009120

    申请日：2011-01-19

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アーゲー

    Inventor： GABRIC ZVONIMIR ,  PAMLER WERNER ,  SCHINDLER GUENTHER ,  STICH ANDREAS

    IPC: H01L23/522 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/768

    CPC classification number: H01L21/7682

    Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing an air gap between conductor tracks that decreases in coupling capacity and is improved in mechanical or electrical characteristics as compared with conventional examples. SOLUTION: A conductor track array includes bases 1 and 2, at least two conductor tracks 4, a cavity 6, and a resist layer 5 covering the conductor tracks 4 to close the cavity 6. A carrier track TB having a width B2 narrower than the width B1 of the conductor tracks 4 is formed to form the air gap for reducing coupling capacity and signal delay by self-alignment technique below the conductor tracks 4 along side faces thereof. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种制造传导轨道之间的空气间隙的方法，其与传统实例相比降低了耦合能力，并提高了机械或电气特性。 解决方案：导体轨道阵列包括基座1和2，至少两个导体轨道4，空腔6和覆盖导体轨道4以封闭空腔6的抗蚀剂层5.具有宽度B2的载体轨道TB 形成比导体轨道4的宽度B1窄的狭缝，以形成气隙，用于通过导电轨道4沿着其侧面的自对准技术降低耦合电容和信号延迟。 版权所有（C）2011，JPO＆INPIT

    Conductive track array and its manufacturing method
    2.
    发明专利
    Conductive track array and its manufacturing method 有权
    导电跟踪阵列及其制造方法

    公开(公告)号：JP2007088439A

    公开(公告)日：2007-04-05

    申请号：JP2006224010

    申请日：2006-08-21

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： GABRIC ZVONIMIR ,  PAMLER WERNER ,  SCHINDLER GUENTHER ,  STICH ANDREAS

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/7682

    Abstract: PROBLEM TO BE SOLVED: To provide a conductive track array with reduced coupling capacity and improved mechanical and electrical properties, and its manufacturing method. SOLUTION: The conductive track array includes substrates 1 and 2, at least two conductive tracks 4, cavity 6, and a resist layer 5 that fills up the cavity 6 and covers the conductive track 4. An air gap to reduce the coupling capacity and signal delay by forming a carrier track TB with width of B2, which is smaller than the width B1 of the conductive track 4, is formed under the conductive track 4 along its side wall using a self-align technology. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供具有降低的耦合能力和改善的机械和电气性能的导电轨道阵列及其制造方法。 解决方案：导电轨道阵列包括衬底1和2，至少两个导电轨道4，空腔6以及填充空腔6并覆盖导电轨道4的抗蚀剂层5。 使用自对准技术，通过形成宽度小于导电轨道4的宽度B1的B2的载体轨道TB，沿着其侧壁形成在导电轨道4的下方的容量和信号延迟。 版权所有（C）2007，JPO＆INPIT

    4.
    发明专利
    未知

    公开(公告)号：DE102005039323B4

    公开(公告)日：2009-09-03

    申请号：DE102005039323

    申请日：2005-08-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GABRIC ZVONIMIR ,  STICH ANDREAS ,  PAMLER WERNER ,  SCHINDLER GUENTHER

    IPC: H01L23/522 ,  H01L21/768

    Abstract: A conduction path arrangement has a substrate (1,2), at least two conduction paths (4), formed adjacent to one another over the substrate, and a cavity which is formed at least between the conduction paths (4), and a dielectric covering layer (5) covering the conduction paths and enclosing the cavity. The support paths (TB) between the substrate (1,2) and the conduction paths (4) are designed to support the conduction paths, in which on the contact surface, a width (B1) of the conduction paths is greater than a width (B2) of the support paths (TB). An independent claim is included for a method for fabrication a conduction path arrangement.

    5.
    发明专利
    未知

    公开(公告)号：DE102004050391B4

    公开(公告)日：2007-02-08

    申请号：DE102004050391

    申请日：2004-10-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHINDLER GUENTHER ,  PAMLER WERNER ,  GABRIC ZVONIMIR ,  UNGER EUGEN ,  TRAVING MARTIN ,  STEINLESBERGER GERNOT ,  STICH ANDREAS

    IPC: H01L21/768 ,  H05K3/00

    Abstract: In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.

    6.
    发明专利
    未知

    公开(公告)号：DE102005047111B3

    公开(公告)日：2007-06-21

    申请号：DE102005047111

    申请日：2005-09-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STICH ANDREAS ,  SCHRENK MICHAEL ,  SCHINDLER GUENTHER ,  ENGELHARDT MANFRED

    IPC: H01L27/08 ,  H01L21/768 ,  H01L21/822

    Abstract: Capacitor has a capacitor electrode (E1) formed on a surface of an intermediate dielectric (1). Another intermediate dielectric (4) is formed on the intermediate dielectric (1) and includes an opening for exposing a part of the capacitor electrode. An electrically conductive diffusion-barrier layer (5) is formed on the surface of the capacitor electrode. Another capacitor electrode (E2) is formed on a surface of a capacitor dielectric (6) and includes only another electrically conductive diffusion-barrier layer (7). One of the capacitor electrodes includes titanium, tantalum, tantalum nitride and/or titanium nitride. An independent claim is also included for a method of manufacturing a metal-insulator-metal capacitor.

    7.
    发明专利
    未知

    公开(公告)号：DE502006006768D1

    公开(公告)日：2010-06-02

    申请号：DE502006006768

    申请日：2006-08-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ENGELHARDT MANFRED ,  STICH ANDREAS ,  SCHINDLER GUENTHER ,  SCHRENK MICHAEL

    IPC: H01G4/33 ,  H01G4/40 ,  H01L21/02 ,  H01L27/13

    Abstract: Capacitor has a capacitor electrode (E1) formed on a surface of an intermediate dielectric (1). Another intermediate dielectric (4) is formed on the intermediate dielectric (1) and includes an opening for exposing a part of the capacitor electrode. An electrically conductive diffusion-barrier layer (5) is formed on the surface of the capacitor electrode. Another capacitor electrode (E2) is formed on a surface of a capacitor dielectric (6) and includes only another electrically conductive diffusion-barrier layer (7). One of the capacitor electrodes includes titanium, tantalum, tantalum nitride and/or titanium nitride. An independent claim is also included for a method of manufacturing a metal-insulator-metal capacitor.

    8.
    发明专利
    未知

    公开(公告)号：DE102004050391A1

    公开(公告)日：2006-05-04

    申请号：DE102004050391

    申请日：2004-10-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHINDLER GUENTHER ,  PAMLER WERNER ,  GABRIC ZVONIMIR ,  UNGER EUGEN ,  TRAVING MARTIN ,  STEINLESBERGER GERNOT ,  STICH ANDREAS

    IPC: H01L21/768 ,  H05K3/00

    Abstract: In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.

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