公开(公告)号：DE102006007993B4

公开(公告)日：2007-11-08

申请号：DE102006007993

申请日：2006-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLIEWER JOERG ,  PROELL MANFRED ,  SCHROEDER STEFAN ,  EGGERS GEORG

IPC: G11C29/14 ,  G11C29/10

Abstract: The device has memory cells addressable by address information in a group of respective cells to alternatively read or write data bits at the addressed cell group by an internal data bus (DB). A number of two-way-switches (MX50-MX53) are provided for selection between two provided elementary test samples of respective test data bits and for setting the selected test data bits at the bus. The switches have a control register (SR) and a branching device (ML2) to assign an individually selectable test sample from the elementary test samples for the data bus.

公开(公告)号：DE102006051591B3

公开(公告)日：2008-04-30

申请号：DE102006051591

申请日：2006-11-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLIEWER JOERG ,  PROELL MANFRED ,  SCHROEDER STEFAN ,  EGGERS GEORG ,  RUF WOLFGANG ,  HAAS HERMANN

IPC: G11C29/48 ,  G11C7/10 ,  G11C11/4093

Abstract: The method involves determining that all data outputs (20) of memory chips (12) lie close to a logical zero, if a signal level at a selected data input (18) of a testing device (10) falls below a preset threshold level. The chips are connected with the selected data input of the testing device, and another determination is made that the data outputs of the chips lie close to a logical one, if the signal level at the input of the testing device exceeds the preset threshold level. An independent claim is also included for a testing device for testing a memory chip comprising data outputs and data inputs.

公开(公告)号：DE102004012629A1

公开(公告)日：2005-10-13

申请号：DE102004012629

申请日：2004-03-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOLLRATH JOERG ,  GNAT MARCIN ,  SCHNEIDER RALF ,  SCHROEDER STEFAN

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/105 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/745 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

Abstract: A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the surface of the semiconductor layer, an insulating layer between the first semiconductor region and the second semiconductor region, a semiconductor strip on the surface of the semiconductor layer, which semiconductor strip overlaps the first semiconductor region and the second semiconductor region and adjoins these. A gate overlaps the semiconductor strip at least in the region of the insulating layer. A gate dielectric insulates the gate from the semiconductor strip the first semiconductor region and the second semiconductor region. The semiconductor strip and the gate being formed such that the semiconductor strip is electrically insulating at a first predetermined gate voltage and is electrically conductive at a second predetermined gate voltagero.

公开(公告)号：DE102006007993A1

公开(公告)日：2007-09-06

申请号：DE102006007993

申请日：2006-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLIEWER JOERG ,  PROELL MANFRED ,  SCHROEDER STEFAN ,  EGGERS GEORG

IPC: G11C29/14 ,  G11C29/10

Abstract: The device has memory cells addressable by address information in a group of respective cells to alternatively read or write data bits at the addressed cell group by an internal data bus (DB). A number of two-way-switches (MX50-MX53) are provided for selection between two provided elementary test samples of respective test data bits and for setting the selected test data bits at the bus. The switches have a control register (SR) and a branching device (ML2) to assign an individually selectable test sample from the elementary test samples for the data bus.

公开(公告)号：DE102004012630A1

公开(公告)日：2005-06-30

申请号：DE102004012630

申请日：2004-03-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOLLRATH JOERG ,  GNAT MARCIN ,  SCHNEIDER RALF ,  SCHROEDER STEFAN

IPC: H01L21/336 ,  H01L21/8242 ,  H01L29/08 ,  H01L29/78 ,  H01L27/105

Abstract: A FET comprises a source (42a), a drain (42b) and a canal region (46) in a substrate (10). The source and/or drain regions are separated from the canal region by a barrier layer (40). The latter consists of a nitride or oxide layer.