公开(公告)号：DE102006007993B4

公开(公告)日：2007-11-08

申请号：DE102006007993

申请日：2006-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLIEWER JOERG ,  PROELL MANFRED ,  SCHROEDER STEFAN ,  EGGERS GEORG

IPC: G11C29/14 ,  G11C29/10

Abstract: The device has memory cells addressable by address information in a group of respective cells to alternatively read or write data bits at the addressed cell group by an internal data bus (DB). A number of two-way-switches (MX50-MX53) are provided for selection between two provided elementary test samples of respective test data bits and for setting the selected test data bits at the bus. The switches have a control register (SR) and a branching device (ML2) to assign an individually selectable test sample from the elementary test samples for the data bus.

公开(公告)号：DE10301480B4

公开(公告)日：2006-04-20

申请号：DE10301480

申请日：2003-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN ,  DOBLER MANFRED ,  EGGERS GEORG

IPC: H01L23/50 ,  H01L21/50 ,  H01L21/60 ,  H01L23/495 ,  H05K3/34

Abstract: The method involves one or more stamping process steps in which at least one pin is stamped out of a base body, especially a lead frame. The pin or a section of the pin is coated with a separate metal coating only after final stamping out of the pin. The end face of the outer end section of the pin is also coated with the metal coating. Independent claims are also included for the following: (a) a housing, especially for semiconducting components (b) and a semiconducting component pin.

公开(公告)号：DE10312497A1

公开(公告)日：2004-10-07

申请号：DE10312497

申请日：2003-03-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EGGERS GEORG ,  SCHNEIDER RALF

IPC: H03K5/07 ,  H03K5/08 ,  H03L7/06 ,  H04L7/08

Abstract: The device (1) provides a synchronization signal of given frequency by selection of the impedance of at least one resonator device (8) within a resonance circuit (17) coupled to a driver device (7) providing the synchronization signal, such that the resonance frequency corresponds to the required synchronization signal frequency. An independent claim for a synchronization clock signal generation method is also included.

公开(公告)号：DE10143764A1

公开(公告)日：2003-03-27

申请号：DE10143764

申请日：2001-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN ,  CORDES ERIC ,  EGGERS GEORG ,  DOBLER MANFRED

IPC: H01L21/60 ,  H01L21/607 ,  H01L23/13 ,  H05K3/34 ,  H01L21/58

Abstract: During attachment, the temperature of memory components (especially micro-capacitors) of the chip, is held below that reached during soldering in a soldering oven.

公开(公告)号：DE10317364B4

公开(公告)日：2005-04-21

申请号：DE10317364

申请日：2003-04-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PROELL MANFRED ,  KLIEWER JOERG ,  SCHNEIDER RALF ,  EGGERS GEORG

IPC: G11C8/02 ,  G11C11/406 ,  G11C5/02 ,  G11C8/10

Abstract: An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.

公开(公告)号：DE10317364A1

公开(公告)日：2004-11-18

申请号：DE10317364

申请日：2003-04-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PROELL MANFRED ,  KLIEWER JOERG ,  SCHNEIDER RALF ,  EGGERS GEORG

IPC: G11C8/02 ,  G11C11/406 ,  G11C5/02 ,  G11C8/10

Abstract: An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.

公开(公告)号：DE10143766A1

公开(公告)日：2003-04-03

申请号：DE10143766

申请日：2001-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EGGERS GEORG ,  CORDES ERIC

IPC: G11C11/406

Abstract: A memory system comprising at least one memory cell in which information can be stored and a refreshing means refreshing the memory cell in predetermined time intervals is provided. In addition, the memory cell comprises a driving means driving the refreshing means in such a way that it only refreshes the memory cell when useful information is stored in the memory cell.

公开(公告)号：DE102006051591B3

公开(公告)日：2008-04-30

申请号：DE102006051591

申请日：2006-11-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLIEWER JOERG ,  PROELL MANFRED ,  SCHROEDER STEFAN ,  EGGERS GEORG ,  RUF WOLFGANG ,  HAAS HERMANN

IPC: G11C29/48 ,  G11C7/10 ,  G11C11/4093

Abstract: The method involves determining that all data outputs (20) of memory chips (12) lie close to a logical zero, if a signal level at a selected data input (18) of a testing device (10) falls below a preset threshold level. The chips are connected with the selected data input of the testing device, and another determination is made that the data outputs of the chips lie close to a logical one, if the signal level at the input of the testing device exceeds the preset threshold level. An independent claim is also included for a testing device for testing a memory chip comprising data outputs and data inputs.

公开(公告)号：DE102004015539A1

公开(公告)日：2005-10-20

申请号：DE102004015539

申请日：2004-03-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HUBER THOMAS ,  MENCK PEGGY ,  EGGERS GEORG

IPC: G01R31/26 ,  G01R31/28 ,  G11C29/12 ,  H01L21/66 ,  H01L23/62 ,  H01L27/105

Abstract: The invention involves a process for heating a semi-conductor component, as well as a semi-conductor component, whereby a device for heating the semi-conductor component is provided on the semi-conductor component.

公开(公告)号：DE10147081C1

公开(公告)日：2003-05-08

申请号：DE10147081

申请日：2001-09-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WIRTH NORBERT ,  SCHEIDER RALF ,  EGGERS GEORG ,  KLIEWER JOERG

IPC: G04F1/00 ,  G11C27/02 ,  H03K5/00 ,  H03K5/08 ,  H03K5/13

Abstract: The present invention provides an apparatus for signaling that a predetermined time value has elapsed, having a device for acquiring and storing the amplitude value of a clock signal at an acquisition instant in the temporal profile of the clock signal. A device is provided for continuously comparing the acquired and stored amplitude value of the clock signal with an instantaneous amplitude value of the clock signal and for outputting a comparison signal which has a first logic state if the instantaneous amplitude value of the clock signal is less than the stored amplitude value and has a second logic state if the instantaneous amplitude value of the clock signal is greater than the stored amplitude value. A device is also provided for counting the number of logic states of the comparison signal which occur after the acquisition instant, and for signaling that the predetermined time value has elapsed if the counted number of logic states is equal to a predetermined number of logic states which corresponds temporally to the predetermined time value.