中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.023 seconds)

    2.
    发明专利
    未知

    公开(公告)号：DE60139622D1

    公开(公告)日：2009-10-01

    申请号：DE60139622

    申请日：2001-06-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STETTER MICHAEL ,  GRELLNER FRANK

    IPC: H01L21/28 ,  H01L21/768 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L29/78

    Abstract: A method and apparatus for forming a direct buried strap for a semiconductor device, in accordance with the present invention, includes forming a gate stack on a semiconductor substrate, and forming a protective layer on sidewalls of the gate stack. The protective layer extends horizontally over a portion of the semiconductor substrate adjacent to the gate stack. A conductive layer is formed over the protective layer and in contact with a gate conductor of the gate stack and in contact with a diffusion region formed in the semiconductor substrate adjacent to the gate conductor. A dielectric layer is formed over the conductive layer, and the dielectric layer is patterned to expose a portion of the conductive layer. The portion of the conductive layer which is exposed includes a portion of the conductive layer over the gate conductor and a portion of the substrate adjacent to the gate conductor. The exposed areas of the conductive layer are silicided to form a direct buried strap and a silicided diffusion region in the substrate. The direct buried strap electrically connects the gate conductor to the diffusion region in a same level of the semiconductor device.

    3.
    发明专利
    未知

    公开(公告)号：DE502004001106D1

    公开(公告)日：2006-09-14

    申请号：DE502004001106

    申请日：2004-04-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FREUND JOHANNES ,  STETTER MICHAEL

    IPC: G03F7/20 ,  G03F20060101 ,  G03F1/00 ,  G03F9/00 ,  H01L23/544

    Abstract: A masking arrangement and method for producing integrated circuit. arrangements are described. The masking arrangement includes a substrate with lithographic patterns. The lithographic patterns are arranged in different partial regions for integrated circuits that have mutually different wiring of components as well as for test patterns. Auxiliary patterns are provided for alignment of multiple lithography planes during production of one of the circuit arrangements either with or without simultaneous production of another of the circuit arrangement. The auxiliary patterns are arranged close to corners of each of the partial regions and contain alignment or overlap marks. The auxiliary patterns and the test pattern for a particular partial region form a frame around the partial region. Filling patterns are present between the partial regions.

    4.
    发明专利
    未知

    公开(公告)号：DE10317893A1

    公开(公告)日：2004-11-11

    申请号：DE10317893

    申请日：2003-04-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STETTER MICHAEL ,  FREUND JOHANNES

    IPC: G03F20060101 ,  G03F1/00 ,  G03F7/20 ,  G03F9/00 ,  H01L23/544

    Abstract: A masking arrangement and method for producing integrated circuit. arrangements are described. The masking arrangement includes a substrate with lithographic patterns. The lithographic patterns are arranged in different partial regions for integrated circuits that have mutually different wiring of components as well as for test patterns. Auxiliary patterns are provided for alignment of multiple lithography planes during production of one of the circuit arrangements either with or without simultaneous production of another of the circuit arrangement. The auxiliary patterns are arranged close to corners of each of the partial regions and contain alignment or overlap marks. The auxiliary patterns and the test pattern for a particular partial region form a frame around the partial region. Filling patterns are present between the partial regions.

    5.
    发明专利
    未知

    公开(公告)号：DE102004010352A1

    公开(公告)日：2004-09-23

    申请号：DE102004010352

    申请日：2004-03-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： COWLEY ANDY ,  HOINKIS MARK ,  KALTALIOGLU ERDEM ,  STETTER MICHAEL

    IPC: H01L21/768

    Abstract: Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.

    6.
    发明专利
    未知

    公开(公告)号：DE102004005697B4

    公开(公告)日：2007-03-29

    申请号：DE102004005697

    申请日：2004-02-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： COWLEY ANDY ,  STETTER MICHAEL ,  KALTALIOGLU ERDEM

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A conductive line is formed in a first insulating layer. A second insulating layer is formed over the conductive line and the first insulating layer. A via extends through the second insulating layer to contact at least the top surface of the conductive line. The via also extends through the first insulating layer to contact at least a top portion of at least one sidewall of the conductive line. The conductive line sidewall may include an outwardly extending hook region, so that a portion of the via is disposed beneath the conductive line hook region, forming a locking region within the via proximate the conductive line hook region.

    7.
    发明专利
    未知

    公开(公告)号：DE102004010352B4

    公开(公告)日：2006-10-19

    申请号：DE102004010352

    申请日：2004-03-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： COWLEY ANDY ,  HOINKIS MARK ,  KALTALIOGLU ERDEM ,  STETTER MICHAEL

    IPC: H01L21/768

    Abstract: Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.

    8.
    发明专利
    未知

    公开(公告)号：DE102004005697A1

    公开(公告)日：2004-08-26

    申请号：DE102004005697

    申请日：2004-02-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： COWLEY ANDY ,  STETTER MICHAEL ,  KALTALIOGLU ERDEM

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A conductive line is formed in a first insulating layer. A second insulating layer is formed over the conductive line and the first insulating layer. A via extends through the second insulating layer to contact at least the top surface of the conductive line. The via also extends through the first insulating layer to contact at least a top portion of at least one sidewall of the conductive line. The conductive line sidewall may include an outwardly extending hook region, so that a portion of the via is disposed beneath the conductive line hook region, forming a locking region within the via proximate the conductive line hook region.

Patent Agency Ranking