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    METHOD FOR TRANSMITTING AN ANALOGUE DATA STREAM WITH AN OPTIMAL ADJUSTMENT OF THE TIME RANGE REGENERATOR
    2.
    发明申请
    METHOD FOR TRANSMITTING AN ANALOGUE DATA STREAM WITH AN OPTIMAL ADJUSTMENT OF THE TIME RANGE REGENERATOR 审中-公开
    方法用于传送模拟数据流的时域均衡器的最佳匹配

    公开(公告)号：WO02103973A3

    公开(公告)日：2003-09-25

    申请号：PCT/EP0206284

    申请日：2002-06-07

    Applicant: INFINEON TECHNOLOGIES AG ,  STRAEUSSNIGG DIETMAR

    Inventor： STRAEUSSNIGG DIETMAR

    IPC: H04L25/03

    CPC classification number: H04L25/03159 ,  H04L25/03012 ,  H04L2025/03414

    Abstract: The invention relates to a method for transmitting an analogue data stream (101), comprising a regeneration process for reducing transient reactions. According to said method, an input signal (xk) is input into a channel transmission unit (103) and into a unit (108) that increases the sampling rate, the signal is regenerated in a regeneration unit (107), the signal that has been conducted via a unit (108) that increases the sampling rate and a delay unit (120) is conducted through a dummy system unit (123), a sampling rate of the signal that has been conducted through the dummy system unit (123) is reduced in a sampling rate reduction unit (124), the signal that is emitted from the sampling rate reduction unit (124) is overlaid with the signal that has been regenerated in the regeneration unit (107) and the overlaid signal is emitted as an error signal (ek) from the second overlay unit (106). The invention also relates to a regeneration for reducing transient reactions in the frequency range, whereby the signal in the frequency range is impinged by an oversampling factor m.

    Abstract translation: 本发明提供一种方法，用于传输模拟数据流（101），所述均衡用于降低瞬变被调整，其特征在于输入信号（X k）的成信道传输单元（103）和上采样单元（108）被输入; 该信号是在均衡部（107）通过上采样单元（108）和延迟单元（120），由一个备用系统单元（123）被传递发送信号均衡; 通过定向信号减小的采样速率由等效系统单元（123）在从下采样单元输出的下采样单元（124）被减少（124）由所述均衡单元（107）均衡的信号被叠加信号，并将该叠加的信号作为一个 从所述第二本地单元（106）的误差信号（EK）被输出。 此外，用于减少在所述频率范围的瞬变的均衡设置，其中，在具有过采样因子m的频域的信号被施加。

    5.
    发明专利
    未知

    公开(公告)号：DE10349739B4

    公开(公告)日：2007-07-12

    申请号：DE10349739

    申请日：2003-10-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PAOLI GERHARD ,  STRAEUSSNIGG DIETMAR ,  NOESSING GERHARD ,  HOHL JOHANNES

    IPC: H04M11/06 ,  H03H17/02 ,  H03H17/06 ,  H04L25/02 ,  H04L27/00 ,  H04L27/04

    Abstract: A method and a device for interpolating or decimating a signal is provided, the signal being processed by a plurality of signal processing means connected in series, which at least comprise means for increasing or reducing a clock rate of the signal and filtering means. To achieve adaptation to different operating modes or transmission standards, individual portions of the signal processing means connected in series can be bridged by bypasses. In addition, filtering parameters of the filtering means can be varied and factors, by which a clock rate of the signal is increased or reduced, can be changed.

    7.
    发明专利
    未知

    公开(公告)号：DE10059135B4

    公开(公告)日：2005-07-14

    申请号：DE10059135

    申请日：2000-11-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FERIANZ THOMAS ,  STRAEUSSNIGG DIETMAR ,  SINGERL PETER ,  ZOJER HERBERT

    IPC: H04L5/02 ,  H04L27/00 ,  H04M11/06 ,  H04L5/06

    Abstract: A transceiver (1) picks up data to be transmitted from a data plated-wire memory via a first data line (3) and writes this data into a register (4). Data to be transmitted is assembled in the data register in data blocks, passed on via second data lines (5) to an encoder (6) to encode it with a Reed Solomon encoding method and converted with Fast Fourier Transformation. The transformed data is then converted to an analog data signal.

    8.
    发明专利
    未知

    公开(公告)号：AT222430T

    公开(公告)日：2002-08-15

    申请号：AT99963242

    申请日：1999-11-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HAUPTMANN JOERG ,  PESSL PETER ,  STRAEUSSNIGG DIETMAR

    IPC: H03H17/04 ,  H03M3/02 ,  H03M7/36

    Abstract: The invention relates to a circuit configuration for quantization of digital signals and for filtering quantization noise. Said circuit configuration comprises a multitude of digital control loops connected in series and having quantizers. The digital signals having a word length of m-bits are fed to a first control loop in the series. The quantization error signal of each quantizer is filtered and fed back to the corresponding digital control loop. It is then fed to a downstream digital control loop. The quantized output signal of the first digital control loop is adapted to a third word length of u-bits which is smaller than the first word length. Except for the quantized output signal of the first digital control loop, the quantized output signals of the digital control loops of the series are respectively filtered by a digital filter. In an adder, said quantized output signals are then added to the first quantized output signal of the first digital control loop of the series to prevent quantization errors. The output signal of the adder has a second word length of n-bits and represents the quantized output signal of the circuit configuration.

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