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    FIELD EFFECT TRANSISTOR STRUCTURE, ASSOCIATED SEMICONDUCTOR STORAGE CELL, AND CORRESPONDING PRODUCTION METHOD
    1.
    发明申请
    FIELD EFFECT TRANSISTOR STRUCTURE, ASSOCIATED SEMICONDUCTOR STORAGE CELL, AND CORRESPONDING PRODUCTION METHOD 审中-公开
    场效应晶体管结构相关半导体存储单元及其相关方法

    公开(公告)号：WO2004047182A3

    公开(公告)日：2004-08-19

    申请号：PCT/DE0303748

    申请日：2003-11-12

    Applicant: INFINEON TECHNOLOGIES AG ,  HIERLEMANN MATTHIAS ,  STRASSER RUDOLF

    Inventor： HIERLEMANN MATTHIAS ,  STRASSER RUDOLF

    IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/102 ,  H01L27/108 ,  H01L29/10 ,  H01L29/78

    CPC classification number: H01L27/108 ,  H01L27/0214 ,  H01L27/1082 ,  H01L27/10844 ,  H01L27/1087

    Abstract: The invention relates to a field effect transistor structure, an associated semiconductor storage cell, and a corresponding production method. A diode-doping area (4) within a semiconductor substrate (1) is embodied with a field effect transistor structure (S/D, 3, K) while an electrically conducting diode-connecting layer (5) connects a control layer (3) of the field effect transistor structure to the diode-doping area (4) so as to create a diode (D), whereby excess charge carriers (L) in the semiconductor substrate (1) can be eliminated such that an undesired body effect is prevented.

    Abstract translation: 本发明涉及一种场效应晶体管结构，相关联的半导体存储器单元和相关联的制造方法，其中用于实现二极管（D），二极管的掺杂区域（4）在半导体衬底（1）具有一个场效应晶体管结构（S / D，3，K）形成 和导电二极管连接层（5）连接的控制层与二极管掺杂区的场效应晶体管结构的（3）（4）。 以这种方式，过量的电荷载流子可以在半导体衬底（1），由此防止不期望的体效应被消除（L）。

    SEMICONDUCTOR MEMORY LOCATION COMPRISING A TRENCH CAPACITOR AND METHOD FOR THE PRODUCTION THEREOF
    3.
    发明申请
    SEMICONDUCTOR MEMORY LOCATION COMPRISING A TRENCH CAPACITOR AND METHOD FOR THE PRODUCTION THEREOF 审中-公开
    根据上述制造坟墓电容器及其方法半导体存储单元

    公开(公告)号：WO02073657A3

    公开(公告)日：2003-05-22

    申请号：PCT/DE0200788

    申请日：2002-03-05

    Applicant: INFINEON TECHNOLOGIES AG ,  GUSTIN WOLFGANG ,  GRUENING VON SCHWERIN ULRIKE ,  TEMMLER DIETMAR ,  SCHREMS MARTIN ,  RONGEN STEFAN ,  STRASSER RUDOLF

    Inventor： GUSTIN WOLFGANG ,  GRUENING VON SCHWERIN ULRIKE ,  TEMMLER DIETMAR ,  SCHREMS MARTIN ,  RONGEN STEFAN ,  STRASSER RUDOLF

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L27/10867 ,  H01L27/10873

    Abstract: According to the invention, a trench capacitor is formed inside a trench (30) that is arranged inside a substrate (20). The trench (30) is filled with a conductive trench filling (50) that serves as an inner capacitor electrode. An epitaxial layer (75) is grown on the lateral wall of the trench (30) on the substrate (20). A buried contact (60) is arranged between the conductive trench filling (50) with the second intermediate layer (65) and the epitaxially grown layer (75). A dopant out-diffusion (80), which is formed while leading out from the buried contact (60), is arranged inside the epitaxially grown layer (75). The epitaxially grown layer (75) enables the dopant out-diffusion (80) to be further removed from a selection transistor (10) located next to the trench whereby permitting the prevention of short channel effects in the selection transistor (10).

    Abstract translation: 它是在一个沟槽30，其被布置在基底20的严重电容器形成 沟槽30填充有导电填充严重50作为内部电容器电极。 在沟槽30的基板20上的侧壁，外延层75生长。 导电填充坟50与第二中间层65和外延生长层75，掩埋接触60布置之间。 在一个Dotierstoffausdiffusion 80被布置在外延生长层75，这是从所述掩埋接触60出来而形成。 通过外延生长层75，Dotierstoffausdiffusion 80进一步远离相邻排列的选择晶体管10，从而短沟道效应可以在选择晶体管10度可以避免沟槽。

    4.
    发明专利
    未知

    公开(公告)号：DE10153110B4

    公开(公告)日：2006-11-30

    申请号：DE10153110

    申请日：2001-10-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HIERLEMANN MATTHIAS ,  STRASSER RUDOLF

    IPC: H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    Abstract: A memory cell (400) comprises trench filled with conductive material; selection transistor; connection (6) connecting the conductive material to selection transistor, the connection including vertical insulation collar; and lateral insulation collar of trench (5). The vertical insulation collar is connected to lateral insulation collar. The lateral insulation collar is configured laterally with respect to vertical insulation collar. Independent claims are also included for: (a) a semiconductor component with at least one memory cell, comprising a trench filler with a conductive material; a selection transistor; a connection; and a lateral insulation collar; and (b) manufacture of lateral insulation collar for a memory cell, comprising fabricating a bottle trench and filling the trench near the vertical wall; subsequently filling an upper, curved region of the trench with an insulator; and anisotropically etching the upper region of the trench to penetrate through the insulator.

    6.
    发明专利
    未知

    公开(公告)号：DE10220653A1

    公开(公告)日：2003-11-27

    申请号：DE10220653

    申请日：2002-05-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STRASSER RUDOLF

    IPC: H01L23/522 ,  H01L23/528 ,  H01L23/66

    Abstract: An explanation is given of an integrated interconnect arrangement having a plurality of interconnects that cross over one another at two crossover sections. By virtue of this measure, it is possible to achieve a uniform current flow in all three interconnects even at very high frequencies.

    Memory cell for dynamic random access memories comprises trench filled with conductive material, selection transistor, and lateral insulation collar of trench
    10.
    发明专利
    Memory cell for dynamic random access memories comprises trench filled with conductive material, selection transistor, and lateral insulation collar of trench 未知

    公开(公告)号：DE10153110A1

    公开(公告)日：2003-05-08

    申请号：DE10153110

    申请日：2001-10-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HIERLEMANN MATTHIAS ,  STRASSER RUDOLF

    IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    Abstract: A memory cell (400) comprises trench filled with conductive material; selection transistor; connection (6) connecting the conductive material to selection transistor, the connection including vertical insulation collar; and lateral insulation collar of trench (5). The vertical insulation collar is connected to lateral insulation collar. The lateral insulation collar is configured laterally with respect to vertical insulation collar. Independent claims are also included for: (a) a semiconductor component with at least one memory cell, comprising a trench filler with a conductive material; a selection transistor; a connection; and a lateral insulation collar; and (b) manufacture of lateral insulation collar for a memory cell, comprising fabricating a bottle trench and filling the trench near the vertical wall; subsequently filling an upper, curved region of the trench with an insulator; and anisotropically etching the upper region of the trench to penetrate through the insulator.

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