公开(公告)号：JP2006295181A

公开(公告)日：2006-10-26

申请号：JP2006107761

申请日：2006-04-10

Applicant: Infineon Technologies Ag ,  インフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG

Inventor： STORBECK OLAF ,  HAHN JENS ,  SCHMIDBAUER SVEN ,  FAUL JUERGEN ,  JAKUBOWSKI FRANK ,  SCHUSTER THOMAS

IPC: H01L21/28 ,  H01L21/20 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/265 ,  H01L21/28044 ,  H01L21/324 ,  H01L29/4925

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a semiconductor device configured by a gate dielectric layer and an impurity semiconductor formed so as to achieve a small gate leak current or at least a suitable gate leak current. SOLUTION: The manufacturing method of a semiconductor includes a step of providing a substrate, a step of forming a dielectric layer on the substrate, a step of growing an amorphous semiconductor layer on the dielectric layer, a step of doping impurity in the amorphous semiconductor layer, and a step of forming a crystallized layer from the amorphous semiconductor by performing a high-temperature process on the amorphous layer. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种形成由栅介质层和杂质半导体构成的半导体器件的方法，其形成为实现小的漏极电流或至少合适的栅极漏电流。 解决方案：半导体的制造方法包括提供衬底的步骤，在衬底上形成电介质层的步骤，在电介质层上生长非晶半导体层的步骤，将掺杂杂质的步骤 非晶半导体层，以及通过对非晶层进行高温处理从非晶半导体形成结晶化层的工序。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO0117019A3

公开(公告)日：2001-05-10

申请号：PCT/DE0002866

申请日：2000-08-23

Applicant: INFINEON TECHNOLOGIES AG ,  TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10861 ,  H01L27/10832

Abstract: The invention comprises a memory with a storage cell (100) that is formed in a substrate (105) and consists of a trench capacitor (110) and a transistor (160). The trench capacitor (110) is connected to the transistor (160) with a self-aligned connection (220). The transistor (160) at least partially covers said trench capacitor (110). The trench capacitor (110) is filled with a conductive trench filling and an insulating cover layer (135) is located on said conductive trench filling (130). An epitaxy layer (245) is located above said insulating cover layer (135). The transistor (160) is formed in said epitaxy layer (245). The self-aligned connection (220) is formed in a contact trench (205) and consists of an insulation collar (235) into which a conductive material (225) is introduced. A conductive cap (230) is formed on said conductive material.

Abstract translation: 本发明包括具有存储单元（100）的存储器，存储单元（100）形成在衬底（105）中并由沟槽电容器（110）和晶体管（160）组成。 沟槽电容器（110）通过自对准端子（220）连接到晶体管（160）。 晶体管（160）至少部分地覆盖沟槽电容器（110）。 沟槽电容器（110）填充有导电沟槽填充物（130），并且在导电沟槽填充物（130）上是绝缘覆盖层（135）。 绝缘覆盖层（135）之上是外延层（245）。 晶体管（160）形成在外延层（245）中。 自对准端子（220）形成在接触沟槽（205）中并且由其中引入导电材料（225）的绝缘轴环（235）组成。 在导电材料上形成导电帽（230）。

公开(公告)号：WO2004025693A3

公开(公告)日：2004-04-29

申请号：PCT/EP0308946

申请日：2003-08-12

Applicant: INFINEON TECHNOLOGIES AG ,  ENDERS GERHARD ,  FAUL JUERGEN ,  FISCHER BJOERN ,  HEINECK LARS ,  HIERLEMANN MATTHIAS ,  POPP MARTIN ,  VOIGT PETER

Inventor： ENDERS GERHARD ,  FAUL JUERGEN ,  FISCHER BJOERN ,  HEINECK LARS ,  HIERLEMANN MATTHIAS ,  POPP MARTIN ,  VOIGT PETER

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8242

CPC classification number: H01L27/10873 ,  H01L21/26586 ,  H01L27/10888 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/66659

Abstract: The invention relates to a method for the production of a semi-conductor structure comprising a plurality of gate stacks (GS1 - GS8) which are arranged on a semi-conductor substrate (1). Said method comprises the following steps: applying the gate-stack (GS1 - GS8) to a gate dielectric (5) via the semi-conductor substrate (1); implanting doping (100, 105, 110, 120, 130; 105''', 110''', 120''', 130''', 140''') which is self-adjusted in relation to the edges of the gate stack (GS1 - GS8); and forming an side wall oxide (40) on the free side walls of the gate stack (GS1 - GS8) while at the same time forming diffused doping areas (100', 110', 120', 130'; 110''', 120''', 130''', 140''') below the gate stack. The invention also relates to said type of semi-conductor structure.

Abstract translation: 本发明提供了一种用于生产具有多个栅极堆栈（GS1 - GS8）的半导体结构的半导体衬底（1）上通过以下步骤制备：将所述栅极堆叠 - 上的栅极电介质（GS1 GS8）（5 ）在半导体衬底上（1）; 注入掺杂剂（100，105，110，120，130; 105 '' '110' ''，120 '''，130' ''，140 ''“）自对准到栅叠层的边缘（GS1 - GS8 ）; 以及形成在所述栅极堆叠（GS1 - GS8）的暴露的侧壁上形成侧壁氧化物（40）与扩散掺杂区的同时形成（100 '110' ，120'，130 '; 110 '''，120' ''，130 “”栅极边缘下”，140' ‘’）。 本发明还提供这样的半导体结构。

公开(公告)号：DE10153200A1

公开(公告)日：2003-05-15

申请号：DE10153200

申请日：2001-10-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  FAUL JUERGEN ,  SCHUSTER THOMAS ,  STAUB RALF

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/316

Abstract: Filling openings in a gate electrode layer on a semiconductor wafer comprises growing a gate oxide layer on the wafer; producing a gate electrode layer on the gate oxide layer; defining opening regions; etching the gate electrode layer up to the gate oxide layer in the opening regions; nitriding the gate oxide layer in the opening regions; and applying a BPSG layer to fill the opening regions. Preferred Features: After exposing the opening regions, an additional oxide layer is thermally produced which is nitrided in a further step. At least one opening region is a source/drain region, in which side wall spacers are exposed in the exposed source/drain region. A source/drain doping is formed in the wafer over the oxide layer in the exposed source/drain region.

公开(公告)号：DE10207740B4

公开(公告)日：2005-08-25

申请号：DE10207740

申请日：2002-02-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FAUL JUERGEN ,  ALSMEIER JOHANN

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L21/336

Abstract: Production of a p-channel field effect transistor on a semiconductor substrate (10) comprises doping the substrate with donators using a first implantation to form an n-doped sink (70), thermally oxidizing to form a thin oxide layer (30) on the surface of the substrate, depositing a first layer (40) made from an n-doped polysilicon, p-doping the first layer with boron or boron fluoride particles, lithographically projecting and etching to remove the first layer, doping the substrate with acceptors using a second implantation (140) to form a p-doped source region, and subjecting the substrate to an elevated temperature. Preferred Features: The step of p-doping the first layer with boron or boron fluoride is carried whilst the first layer is deposited. The first layer is p-doped using a third implantation after depositing the fist layer.

公开(公告)号：DE10250872A1

公开(公告)日：2004-05-19

申请号：DE10250872

申请日：2002-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AMON JUERGEN ,  FAUL JUERGEN ,  GRUENING ULRIKE ,  JAKUBOWSKI FRANK ,  SCHUSTER THOMAS ,  STRASSER RUDOLF

IPC: H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242

Abstract: Gate stacks (GS1-4) are applied to a gate dielectric (11) over the semiconductor substrate (10). A sidewall oxide (17) is formed on the gate stacks. A mask (12) is applied to the semiconductor structure, and is then structured. A contact doping (13) is implanted and self-adjusts to the sidewall oxide of the gate stack (GS1, GS2), in regions not covered by the mask

公开(公告)号：DE10240429A1

公开(公告)日：2004-03-18

申请号：DE10240429

申请日：2002-09-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  ENDERS GERHARD ,  HEINECK LARS ,  VOIGT PETER ,  HIERLEMANN MATTHIAS ,  FISCHER BJOERN ,  FAUL JUERGEN

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8242

Abstract: Production of a semiconductor structure comprises applying gate stacks (GS1-GS8) onto a gate dielectric (5) over a semiconductor substrate (1), implanting a dopant (100) which is self-adjusting to the edges of the gate stack, and forming a side wall oxide (40) on exposed side walls of the gate stack with simultaneous formation of diffused doping regions (100', 110', 120', 130') under the gate edge. An Independent claim is also included for a semiconductor structure produced by the above process.

公开(公告)号：DE102004025112B4

公开(公告)日：2008-04-10

申请号：DE102004025112

申请日：2004-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAM ANDREAS ,  ECKART UDO ,  SACHSE HERMANN ,  FAUL JUERGEN

IPC: H01L21/336 ,  H01L21/027 ,  H01L21/265 ,  H01L21/266 ,  H01L21/762 ,  H01L29/10 ,  H01L29/78

公开(公告)号：DE19941148B4

公开(公告)日：2006-08-10

申请号：DE19941148

申请日：1999-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  BENZINGER HERBERT ,  KARCHER WOLFRAM ,  PUSCH CATHARINA ,  SCHREMS MARTIN ,  FAUL JUERGEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.

公开(公告)号：DE10034942A1

公开(公告)日：2002-01-31

申请号：DE10034942

申请日：2000-07-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CURELLO GUISEPPE ,  FAUL JUERGEN

IPC: H01L21/20 ,  H01L21/74 ,  H01L21/8238 ,  H01L29/36 ,  H01L21/324

Abstract: A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process uses individual process steps that are already used in the mass production of integrated circuits and accordingly can be configured for a high throughput.