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    Production of an integrated circuit comprises forming a first metallizing region, forming insulating regions, producing a conducting region, forming a contact in one insulating region and providing a conducting pathway
    1.
    发明专利
    Production of an integrated circuit comprises forming a first metallizing region, forming insulating regions, producing a conducting region, forming a contact in one insulating region and providing a conducting pathway 未知

    公开(公告)号：DE10121240C1

    公开(公告)日：2002-06-27

    申请号：DE10121240

    申请日：2001-04-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TEWS RENE ,  SCHMIDBAUER SVEN

    IPC: H01L23/525 ,  H01L21/768

    Abstract: Production of an integrated circuit comprises forming a first metallizing region (3) made from a first metal in a switching substrate (1); forming a first insulating region (4) on the first metallizing region; producing a conducting region (5') made from a metal silicide on the insulating region; forming a second insulating region on the first insulating region and the conducting region; forming a contact (9) in the second insulating region to contact the conducting region; and providing a conducting pathway (110) for electrically connecting the contact. Production of an integrated circuit comprises forming a first metallizing region (3) made from a first metal in a switching substrate (1); forming a first insulating region (4) on the first metallizing region; producing a conducting region (5') made from a metal silicide on the insulating region; forming a second insulating region on the first insulating region and the conducting region; forming a contact (9) in the second insulating region to contact the conducting region; and providing a conducting pathway (110) for electrically connecting the contact. The conducting region is produced by providing a stack made from a silicon region and a second metallizing region on the first insulating region and tempering the stack. The first insulating region and the silicon region are produced by depositing and structuring using a mask. The second metallizing region is produced by depositing on the structured first insulating region and the silicon region. After tempering the stack, metal remaining on the conducting region is removed by selectively etching. Preferred Features: The metal silicide is NiSi, TiSi or CoSi. The circuit forms an anti-fuse structure.

    3.
    发明专利
    未知

    公开(公告)号：DE10030444A1

    公开(公告)日：2002-01-10

    申请号：DE10030444

    申请日：2000-06-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TEWS RENE ,  LEHR MATTHIAS

    IPC: H01L23/525 ,  H01L21/768 ,  H01L21/28

    Abstract: Dielectric antifuse structures are fabricated by providing an oxide layer having first contact holes for contacts and second contact holes for antifuse structures. A dielectric layer (9) is formed on a surface of the oxide layer. Fabrication of dielectric antifuse structures involves providing an oxide layer (4) having first contact holes for contacts and second contact holes for antifuse structures, forming a dielectric layer on a surface of the oxide layer, applying an organic antireflection layer to the dielectric layer, and applying a resist layer on the organic antireflection layer. The resist layer is lithographically patterned where the second contact holes remain covered with the resist layer. The organic antireflection layer is etched through openings in the resist layer above the first contact holes. The oxide layer is etched through openings in the organic antireflection layer to produce interconnect structures. Residues of the antireflection layer are etched in the first contact holes. An uncovered part of the dielectric layer is etched in the first contact holes then the resist layer and underlying segments of the organic antireflection layer are removed. A second conductive layer (8b) is deposited on the segments of the dielectric layer of the antifuse structures.

    4.
    发明专利
    未知

    公开(公告)号：DE10030442B4

    公开(公告)日：2006-01-12

    申请号：DE10030442

    申请日：2000-06-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LEHR MATTHIAS ,  TEWS RENE ,  MUELLER JOCHEN ,  LINDOLF JUERGEN

    IPC: H01L21/28 ,  H01L23/525 ,  H01L23/532

    Abstract: Connecting element consists of a layer structure (1) arranged between two conducting structures. The layer structure is formed by a dielectric layer (2) which can be destroyed by applying a voltage and a silicon layer (3). The dielectric layer borders a first structure made of tungsten. Preferred Features: The dielectric layer is made of Si3N4 or SiO2. The silicon layer is made of amorphous silicon or polysilicon. The first structure made of tungsten is formed from a first conducting pathway (4) with the dielectric layer applied to its upper side.

    6.
    发明专利
    未知

    公开(公告)号：DE10030445A1

    公开(公告)日：2002-01-10

    申请号：DE10030445

    申请日：2000-06-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TEWS RENE ,  LEIBERG WOLFGANG ,  RUF ALEXANDER ,  LEHR MATTHIAS ,  DRESCHER DIRK

    IPC: H01L23/525

    Abstract: The connection element in an integrated circuit has a layer structure arranged between two conductive structures. The layer structure has a dielectric layer which can be destroyed by application of a predetermined voltage. At least one conductive structure is composed of tungsten. The conductive structure adjoins a conductive layer made of tungsten or a tungsten compound, which is a constituent part of the layer structure and which adjoins the dielectric layer.

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