公开(公告)号：WO02075810A2

公开(公告)日：2002-09-26

申请号：PCT/DE0200822

申请日：2002-03-07

Applicant: INFINEON TECHNOLOGIES AG ,  LEHR MATTHIAS UWE ,  MOECKEL JENS ,  TOEBBEN DIRK

Inventor： LEHR MATTHIAS UWE ,  MOECKEL JENS ,  TOEBBEN DIRK

IPC: H01L21/82 ,  H01L23/525 ,  H01L23/528

CPC classification number: H01L23/5256 ,  H01L23/525 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A first electric connecting element (15) and a second electric connecting element (20) are placed next to one another on a substrate (5) along a first direction (Y). The first electric connecting element (15) is located at a first distance (35) from the second electric connecting element (20). A first conductor track (40) and a second conductor track (45) are placed on the substrate (5), and the first conductor track (40) is connected to the first electric connecting element (15), and the second conductor track (45) is connected to the second electric connecting element (20). A third electric connecting element (25) and a fourth electric connecting element (30) are placed on the substrate (5), and the first conductor track (40) and the second conductor track (45) are placed between the third electric connecting element (25) and the fourth electric connecting element (30) and, at this location, are located at a second distance (50) from one another that is less than the first distance (35).

Abstract translation: 上的基板（5）的第一电连接元件（15）和沿一第一方向（Y）的第二电连接元件（20）并排布置。 第一电连接件（15）具有第一距离（35）到第二电连接元件（20）。 第一导体轨道（40）和第二导体线路（45）被布置在所述基板（5）和第一导体轨道（40）被连接到所述第一电连接元件（15）和第二导体（45）上被连接到第二电连接元件 （20）。 它是在基板（5）和第一导体轨道（40）和所述第三电连接件（25）和第四之间的第二导体（45）上的第三电连接件（25）和第四电连接件（30） 布置的电连接元件（30），并具有从那里彼此的第二距离（50），其是大于所述第一距离（35）小。

公开(公告)号：DE10043215C1

公开(公告)日：2002-04-18

申请号：DE10043215

申请日：2000-09-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHR MATTHIAS UWE ,  POLEI VERONIKA ,  SPERL IRENE ,  SCHILLING UWE

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/525 ,  H01L21/768

Abstract: A method for producing antifuse structures and antifuses by which adjacent conductive regions can be selectively electrically connected involve the application of a sacrificial layer to a first conductive region. The sacrificial layer is patterned with the aid of a photolithographic method. A fuse layer is applied and the sacrificial layer is then removed. A non-conductive layer is applied and a conductive material is introduced in an opening in the non-conductive layer for the purpose of forming a second conductive region.

公开(公告)号：DE19939852A1

公开(公告)日：2001-03-15

申请号：DE19939852

申请日：1999-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUCH LOTHAR ,  ZELL THOMAS ,  LEHR MATTHIAS UWE ,  KIESLICH ALBRECHT

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/28

Abstract: Stacked vias are produced by introducing metal islands that are referred to as landing pads in order to establish a contact between superimposed stacks. Due to the line shortening effect, said landing pads substantially project laterally over the vias. According to the invention, vias that are located in superimposed layers are off-set laterally. The inventive landing pad is substantially configured as a track that extends between the vias. The contact surfaces provided at the end of the track can be chosen smaller than the square contact surfaces of conventional metal islands since the line shortening effect is less critical for longer tracks. The inventive structures save space and can be more easily accommodated in a circuit layout to be miniaturized, thereby resulting in an increased shrink factor of the semiconductor structure.

公开(公告)号：DE10112543A1

公开(公告)日：2002-10-02

申请号：DE10112543

申请日：2001-03-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOECKEL JENS ,  TOEBBEN DIRK ,  LEHR MATTHIAS UWE

IPC: H01L21/82 ,  H01L23/525 ,  H01L23/528

Abstract: A first electric connecting element (15) and a second electric connecting element (20) are placed next to one another on a substrate (5) along a first direction (Y). The first electric connecting element (15) is located at a first distance (35) from the second electric connecting element (20). A first conductor track (40) and a second conductor track (45) are placed on the substrate (5), and the first conductor track (40) is connected to the first electric connecting element (15), and the second conductor track (45) is connected to the second electric connecting element (20). A third electric connecting element (25) and a fourth electric connecting element (30) are placed on the substrate (5), and the first conductor track (40) and the second conductor track (45) are placed between the third electric connecting element (25) and the fourth electric connecting element (30) and, at this location, are located at a second distance (50) from one another that is less than the first distance (35).

公开(公告)号：DE10103298A1

公开(公告)日：2002-08-22

申请号：DE10103298

申请日：2001-01-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ALSMEIER JOHANN ,  LEHR MATTHIAS UWE

IPC: H01L23/525

Abstract: Integrated anti-fuse structure (1) comprises: a dielectric layer (11); conducting contact layers (12); and aluminum layers (10) bordering the dielectric layer. Preferred Features: At least one of the aluminum layers is arranged between the dielectric layer and a tungsten contact (22), or between the dielectric layer and one of the conducting contact layers. The conducting contact layer is made from tungsten-silicon or poly-silicon. The dielectric layer is made from silicon nitride.

公开(公告)号：DE10054969A1

公开(公告)日：2002-03-28

申请号：DE10054969

申请日：2000-11-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEIBERG WOLFGANG ,  BAUCH LOTHAR ,  LEHR MATTHIAS UWE

IPC: C23F4/00 ,  H01L21/311 ,  H01L21/314 ,  H01L21/3213

Abstract: Structuring metal layers by lithography, especially i-line lithography or DIN lithography and subsequent plasma etching, especially reactive ion etching, comprises applying the required antireflection layer (3) as a dielectric layer before the reactive ion etching of the uppermost metal layer of several metal layers placed on top of each other. Preferred Features: The thickness of the dielectric antireflection layer is chosen so that the light used in the lithographic process undergoes minimal reflection. The dielectric antireflection layer forms a highly selective etching mask in combination with a thin photoresist layer (4). The antireflection layer comprises silicon oxy nitride.

公开(公告)号：DE19945425A1

公开(公告)日：2001-04-19

申请号：DE19945425

申请日：1999-09-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEIBERG WOLFGANG ,  BAUCH LOTHAR ,  LEHR MATTHIAS UWE ,  LUEKEN ELKE ,  MOLL PETER ,  VOGT MIRKO ,  KIESLICH ALBRECHT

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/321 ,  G03F7/20

Abstract: Structuring a metal layer (M) during semiconductor finishing comprises applying a lacquer layer (L) to a semiconductor substrate; structuring the lacquer layer using lithography and producing an etching mask; and structuring the metal layer using the mask. Initially a hard mask is applied to the metal layer and the lacquer layer is applied to the mask, where the lacquer layer is thin so that only the mask and not the metal layer can be structured with the aid of the lacquer layer. The hard mask is structured to form an etching mask with the aid of the structured lacquer layer. The metal layer is structured with the hard mask as an etching mask. Preferred Features: The hard mask has a first layer (H1) of an oxide, preferably silicon dioxide, and a second layer (H2) to reduce reflection and made of silicon nitride. The metal layer is made of aluminum and/or copper.

公开(公告)号：DE19939852B4

公开(公告)日：2006-01-12

申请号：DE19939852

申请日：1999-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUCH LOTHAR ,  ZELL THOMAS ,  LEHR MATTHIAS UWE ,  KIESLICH ALBRECHT

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: In the fabrication of stacked vias, metal islands referred to as landing pads are introduced for the purpose of contact-connection between the vias that are arranged one above the other. The metal islands project laterally beyond the vias to a significant extent on account of the line shortening effect. The vias arranged in layers lying one above the other are laterally offset with respect to one another. The landing pad of the invention is configured as an interconnect running between the vias. On account of the line shortening effect, which is less critical for longer tracks, contact areas provided at the ends of the interconnect do not have to be chosen to be as large as the square contact areas of conventional metal islands and can therefore be accommodated to save more space on a circuit layout to be miniaturized. The shrink factor of such a semiconductor structure is increased.

公开(公告)号：DE10053915C2

公开(公告)日：2002-11-14

申请号：DE10053915

申请日：2000-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHR MATTHIAS UWE ,  TEWS RENE ,  VOGT MIRKO

IPC: H01L21/3213 ,  H01L21/768

公开(公告)号：DE10107666C1

公开(公告)日：2002-08-14

申请号：DE10107666

申请日：2001-02-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AYADI KAMEL ,  MUELLER JOCHEN ,  LINDOLF JUERGEN ,  SAVIGNAC DOMINIQUE ,  DANKOWSKI STEFAN ,  LEHR MATTHIAS UWE ,  BRINTZINGER AXEL ,  FREY ULRICH

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/522

Abstract: The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15') above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15') in order to uncover the surface of the first insulating layer (25); forming a contact (11a') in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15'); and providing an interconnect (40a) for electrical connection of the contact (11a').