公开(公告)号：JP2001257160A

公开(公告)日：2001-09-21

申请号：JP2001004180

申请日：2001-01-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EBERTSEDER EVA ,  LEHR MATTHIAS ,  WERNEKE TORSTEN ,  HANEBECK JOCHEN ,  PAHLITZSCH JURGEN

IPC: G03F9/00 ,  H01L21/027 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/544

Abstract: PROBLEM TO BE SOLVED: To make an alignment mark produceable without requiring much labor and, at the same time, surely detectable by means of a measuring apparatus. SOLUTION: A contact hole 4 and an alignment groove 5 are formed through an insulating layer 2 by etching the layer 2 until the bottoms of the hole 4 and groove 5 reach a first metallic layer 3, and a metal 6 is caused to deposit in the groove 5 and hole 4. Continuously, the surface of the metal 6 is caused to subside within the positioned extent of the groove 5 by the CMP method, so as to form a profile for the alignment mark formed on a second metallic layer 9 caused to deposit on the insulating layer 2.

公开(公告)号：WO0237557A3

公开(公告)日：2002-08-01

申请号：PCT/EP0111076

申请日：2001-09-25

Applicant: INFINEON TECHNOLOGIES AG ,  KARCHER WOLFRAM ,  LEHR MATTHIAS ,  ZEILER DIETER

Inventor： KARCHER WOLFRAM ,  LEHR MATTHIAS ,  ZEILER DIETER

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/3205

CPC classification number: H01L28/40 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a method for producing an integrated circuit, comprising the following steps: a circuit substrate (1) is prepared; a first metallising area (10a) and a second metallising area (10b) consisting of a first metal are provided in the circuit substrate (1); an intermediate layer (15) is provided over the first metallising area (10a) and the second metallising area (10b); the intermediate layer (15) over the first metallising area (10a) is removed by etching, an oxide film (100) being simultaneously formed on the surface of the first metallising area (10a); and the oxide film (100) on the surface of the first metallising area (10a) is at least partially transformed so that a conductive compound is created from the first metal, by means of the oxide film (100), forming a connection to the first metallising area (10a) on the surface of the resulting structure.

Abstract translation: 本发明提供了一种集成电路制造方法，包括以下步骤：提供电路衬底（1）; 在所述电路基板（1）中提供第一金属化区域（10a）和第二金属化区域（10b）; 在第一金属化区域（10a）和第二金属化区域（10b）上提供中间层（15）; 通过蚀刻工艺在第一金属化区域（10a）上去除中间层（15），同时在第一金属化区域（10a）的表面上形成氧化物膜（100）; 和第一金属化（10A）的表面上至少部分地将所述氧化膜（100），从而通过氧化膜（100）中的第一金属的导电连接形成，其具有将所得的表面上的第一金属化（10A）的连接 结构形式。

公开(公告)号：DE10032282A1

公开(公告)日：2002-01-24

申请号：DE10032282

申请日：2000-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUCH LOTHAR ,  LEHR MATTHIAS ,  LEIBERG WOLFGANG ,  SPINLER STEFAN

IPC: G03F7/09 ,  H01L21/311 ,  H01L21/768 ,  G03F7/20

Abstract: Lithographic exposure and structuring comprises preparing a substrate (1); applying an anti-refection layer (4) made up of several layers on the substrate; applying a material layer (2) to be treated on the anti-reflection layer; applying a photoresist layer (3) directly to the material layer; and exposing and structuring the photoresist layer so that the material layer is exposed in pre-determined sections for local selective treatment. An Independent claim is also included for the production of a metallic conducting pathway comprising forming a structured photoresist layer as above; removing the material layer in the exposed sections; optionally carrying out the previous two steps; depositing metallic conducting pathway material in the etched recess; and optionally back-polishing the metallic material. Preferred Features: The anti-refection layer is a SiON layer and the material layer is a SiO2 or nitride layer.

公开(公告)号：DE10030444A1

公开(公告)日：2002-01-10

申请号：DE10030444

申请日：2000-06-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEWS RENE ,  LEHR MATTHIAS

IPC: H01L23/525 ,  H01L21/768 ,  H01L21/28

Abstract: Dielectric antifuse structures are fabricated by providing an oxide layer having first contact holes for contacts and second contact holes for antifuse structures. A dielectric layer (9) is formed on a surface of the oxide layer. Fabrication of dielectric antifuse structures involves providing an oxide layer (4) having first contact holes for contacts and second contact holes for antifuse structures, forming a dielectric layer on a surface of the oxide layer, applying an organic antireflection layer to the dielectric layer, and applying a resist layer on the organic antireflection layer. The resist layer is lithographically patterned where the second contact holes remain covered with the resist layer. The organic antireflection layer is etched through openings in the resist layer above the first contact holes. The oxide layer is etched through openings in the organic antireflection layer to produce interconnect structures. Residues of the antireflection layer are etched in the first contact holes. An uncovered part of the dielectric layer is etched in the first contact holes then the resist layer and underlying segments of the organic antireflection layer are removed. A second conductive layer (8b) is deposited on the segments of the dielectric layer of the antifuse structures.

公开(公告)号：DE10030442B4

公开(公告)日：2006-01-12

申请号：DE10030442

申请日：2000-06-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHR MATTHIAS ,  TEWS RENE ,  MUELLER JOCHEN ,  LINDOLF JUERGEN

IPC: H01L21/28 ,  H01L23/525 ,  H01L23/532

Abstract: Connecting element consists of a layer structure (1) arranged between two conducting structures. The layer structure is formed by a dielectric layer (2) which can be destroyed by applying a voltage and a silicon layer (3). The dielectric layer borders a first structure made of tungsten. Preferred Features: The dielectric layer is made of Si3N4 or SiO2. The silicon layer is made of amorphous silicon or polysilicon. The first structure made of tungsten is formed from a first conducting pathway (4) with the dielectric layer applied to its upper side.

公开(公告)号：DE10054936C1

公开(公告)日：2002-04-25

申请号：DE10054936

申请日：2000-11-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KARCHER WOLFRAM ,  ZEILER DIETER ,  LEHR MATTHIAS

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522

Abstract: Production of an integrated circuit comprises preparing a circuit substrate (1); providing a first metallizing region (10a) and a second metallizing region (10b) from a first metal in the substrate; providing an intermediate layer (15') over the metallizing regions; removing the intermediate layer by etching to form an oxide film (100') above the first metallizing region; and partially converting the oxide film to produce a conducting connection of a first metal and form a connection to the first metallizing region on the surface of the resulting structure. Conversion of the oxide film is carried out using CVD with a gas containing the first metal and a halogen. Preferred Features: The intermediate layer is structured so that it forms a connection to the second metallizing region on the surface of the resulting structure. The first metal is tungsten and the gas is WF6.

公开(公告)号：DE10030445A1

公开(公告)日：2002-01-10

申请号：DE10030445

申请日：2000-06-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEWS RENE ,  LEIBERG WOLFGANG ,  RUF ALEXANDER ,  LEHR MATTHIAS ,  DRESCHER DIRK

IPC: H01L23/525

Abstract: The connection element in an integrated circuit has a layer structure arranged between two conductive structures. The layer structure has a dielectric layer which can be destroyed by application of a predetermined voltage. At least one conductive structure is composed of tungsten. The conductive structure adjoins a conductive layer made of tungsten or a tungsten compound, which is a constituent part of the layer structure and which adjoins the dielectric layer.

公开(公告)号：DE10021098C1

公开(公告)日：2001-09-20

申请号：DE10021098

申请日：2000-04-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHR MATTHIAS ,  LEIBERG WOLFGANG

IPC: H01L21/768 ,  H01L23/525

Abstract: Production of conducting pathways on an integrated chip comprises: (i) applying a stacked dielectric layer; (ii) carrying out photolithography to define contact holes (30); (iii) etching the holes; (iv) applying conducting material and removing outside of the holes; (v) applying an insulating layer (50); (vi) carrying out photolithography to define conducting pathways; (vii) etching conducting pathway trenches (80); and (viii) applying conducting material and removing outside of the trenches. Production of conducting pathways on an integrated chip comprises: (a) applying a stacked dielectric layer consisting of a lower (21) and an upper dielectric layer (22) with an antireflection layer (60) arranged between them; (b) carrying out photolithography to define contact holes (30) in the dielectric layer; (c) etching the holes in the stacked layer; (d) applying conducting material and removing the material outside of the holes so that recesses (40) are formed over the contact holes; (e) applying an insulating layer (50); (f) carrying out photolithography to define conducting pathways in the region of individual contact holes on the insulating layer; (g) etching conducting pathway trenches (80) in the insulating layer and the upper dielectric layer lying underneath so that the antireflection layer acts as an etch stop; and (h) applying conducting material and removing the material outside of the trenches and the recesses over the contact holes. Preferred Features: The insulating layer is made from silicon nitride. The antireflection layer is a light-absorbing inorganic material, especially silicon oxynitride. Polycrystalline silicon is used to fill the contact holes and tungsten is used to fill the trenches and the recesses above the contact holes.

公开(公告)号：DE10000759C1

公开(公告)日：2001-05-23

申请号：DE10000759

申请日：2000-01-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEBECK JOCHEN ,  PAHLITZSCH JUERGEN ,  EBERTSEDER EVA ,  WERNEKE TORSTEN ,  LEHR MATTHIAS

IPC: G03F9/00 ,  H01L21/027 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/544 ,  H01L21/8242 ,  H01L21/768

Abstract: Production of justifying marks in a structure with integrated circuits comprises applying a first planar metal layer (3) over a semiconductor substrate (1) with integrated circuits; applying an insulating layer (2) to the metal layer; etching contact holes and justifying trenches in the insulating layer; inserting metal (6) into the trenches and contact holes and treating the surface of the insulating layer by chemical-mechanical polishing; and depositing a second metal layer (9) onto the insulating layer to produce recesses (8) which form the justifying marks. Preferred Features: The first metal layer is made of AlCu. The second metal layer is made of W. The insulating layer consists of an oxide layer made of SiO2.

公开(公告)号：DE19903195B4

公开(公告)日：2005-05-19

申请号：DE19903195

申请日：1999-01-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHR MATTHIAS

IPC: H01L21/768 ,  H01L21/316 ,  H01L21/324

Abstract: A method for improving the quality of metal conductor tracks on semiconductor structures of wafers, includes covering each metallizing plane, after being deposited and structured, by an interlevel dielectric. An integrated annealing or tempering is performed at the beginning of the deposition of the interlevel dielectric. The quality of metal conductor tracks on semiconductor structures is improved by preventing the recreation of voids and a considerable shortening of the process time is achieved.