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公开(公告)号:DE10245548A1
公开(公告)日:2004-04-15
申请号:DE10245548
申请日:2002-09-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor: ROEMER ANDREAS , HOLLATZ MARK , THIEME PETER
IPC: B24B37/013 , B24B49/02 , H01L21/302 , B24B37/04
Abstract: A polishing device has first and second holding devices (C1-C40 for receiving first and second semiconductor wafers (W1-W4), in which the first wafer is pushed by the first holding device and the second wafer by the second holding device against one polishing surface (P) of a polishing plate (T) and are polished by relative movements to the polishing surface (P). A control device (R) individually adjusts the polishing process parameter for the first and/or second semiconductor wafer (C1-C4) so as to compensate the differences between the first and second semiconductor wafers (W1-W4) as conditioned by the difference in the polishing performance of the two semiconductor wafers (W1-W4). An Independent claim is included for a polishing method.
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公开(公告)号:DE19944304C2
公开(公告)日:2001-09-20
申请号:DE19944304
申请日:1999-09-15
Applicant: INFINEON TECHNOLOGIES AG
Inventor: UWE MATTHIAS , KIESLICH ALBRECHT , THIEME PETER , VOLAND LARS
IPC: H01L21/3105 , H01L23/528 , H01L27/108
Abstract: The semiconductor structure has a layer structure formed from a metalization layer and a dielectric layer. The metalization layer is patterned and has contact areas. The dielectric layer is composed of a depositable material and covers the metalization layer. The contact areas are formed from many contiguous individual structures, which are so narrow that the depositable material does not form, over the individual structures, any areas which run parallel to the metalization layer. The grid of contiguous individual structures forms a contact area which causes dielectric layer elevations which are particularly low and therefore easy to planarize.
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公开(公告)号:DE10356519A1
公开(公告)日:2005-07-07
申请号:DE10356519
申请日:2003-12-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor: GUITTET PIERRE-YVES , MANTZ ULRICH , THIEME PETER , DRUMMER HEIKE
Abstract: A process to determine a geometric shape on the surface of a semiconductor layer, as for integrated circuits, comprises irradiating the layer with radiation of a wavelength at which the layer is transparent, measuring the reflection or transmission from the layer and determining the position of the shape from the image received. An independent claim is also included for an optical system for the above process.
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公开(公告)号:DE19938781B4
公开(公告)日:2004-09-09
申请号:DE19938781
申请日:1999-08-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor: THIEME PETER , RICHTER ANDRE
IPC: B24B53/007 , B24B53/017 , B24B53/12 , H01L21/304 , B24B37/00
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公开(公告)号:DE10059345A1
公开(公告)日:2002-06-13
申请号:DE10059345
申请日:2000-11-29
Applicant: INFINEON TECHNOLOGIES AG , SPEEDFAM IPEC GMBH
Inventor: THIEME PETER , HOLLATZ MARK , REINHOLD FRANK , RIEMER KONSTANTIN
IPC: B24B37/30 , B24B37/32 , H01L21/3105 , H01L21/687 , H01L21/302 , B24B7/22 , B24B37/04 , H01L21/68
Abstract: The device has a base body (4) with a first main surface (9), a guide ring (7) attached to the base body and protruding above the main surface by a first height (11), a step (5) arranged laterally to the main surface next to the guide ring and protruding above the main surface by a second height (12) and a sealing film (6) arranged on the first main surface of the base body and on the step.
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公开(公告)号:DE19938781A1
公开(公告)日:2001-03-01
申请号:DE19938781
申请日:1999-08-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor: THIEME PETER , RICHTER ANDRE
IPC: B24B53/007 , B24B53/017 , B24B53/12 , H01L21/304 , B24B37/00
Abstract: The grinding disk has diamond on its surface, in the form of a naturally grown diamond layer, grown on a semiconductor substrate. The diamond layer is firmly bonded to prevent damage to the CMP pads and to the semiconductor substrate due to diamond pieces getting into polishing pads. The diamond layer has a surface roughness of up to 200 micrometer. The diamond covered substitute surfaces are arranged on a form a uniform radius of the grinding disk. Substrate surfaces are adhered to a support plate made of ceramic or steel.
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公开(公告)号:DE10109328A1
公开(公告)日:2002-09-12
申请号:DE10109328
申请日:2001-02-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SELL BERNHARD , SAENGER ANNETTE , THIEME PETER , DRUMMER HEIKE
IPC: H01L21/304 , H01L21/306 , H01L21/3105 , H01L21/311 , H01L21/768 , H01L21/3213
Abstract: The invention relates to a semiconductor substrate (1) on which a first layer (2), a second layer (3) and a third layer (4) are disposed. The third layer (4) is for example a lacquer mask that is used to structure the second layer (3). The second layer (3) is for example a structured hard mask that is used to structure the first layer (2). The third layer (4) is then removed and a fourth layer (8) is deposited. The fourth layer (8) is for example an insulator that fills the trenches formed in the first layer (2). The fourth layer (8) is then planarized in a CMP step, and planarization is continued while the second layer (3) that is for example a hard mask is removed from the first layer (2) together with the fourth layer (8), thereby leaving the fourth layer (8) in a trench (7) that is disposed in the first layer (2).
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公开(公告)号:DE19944304A1
公开(公告)日:2001-04-05
申请号:DE19944304
申请日:1999-09-15
Applicant: INFINEON TECHNOLOGIES AG
Inventor: UWE MATTHIAS , KIESLICH ALBRECHT , THIEME PETER , VOLAND LARS
IPC: H01L21/3105 , H01L23/528 , H01L27/108
Abstract: The semiconductor structure has a layer structure formed from a metallic layer deposition (1) and a dielectric layer (2). The metallic layer deposition is structured and includes contact surface areas (3). The dielectric layer is composed of a removable material and covers the metallic layer deposition. The contact surface areas are formed from many connected single structures (4) which are so narrow, that the removable material forms no surface areas on the single structures, which proceed parallel to the metallic layer deposition. The single structures are preferably narrower than the double thickness, with which the dielectric layer is layered between structures of the metallic layer deposition.
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