Semiconductor wafer polishing device,

    公开(公告)号:DE10245548A1

    公开(公告)日:2004-04-15

    申请号:DE10245548

    申请日:2002-09-30

    Abstract: A polishing device has first and second holding devices (C1-C40 for receiving first and second semiconductor wafers (W1-W4), in which the first wafer is pushed by the first holding device and the second wafer by the second holding device against one polishing surface (P) of a polishing plate (T) and are polished by relative movements to the polishing surface (P). A control device (R) individually adjusts the polishing process parameter for the first and/or second semiconductor wafer (C1-C4) so as to compensate the differences between the first and second semiconductor wafers (W1-W4) as conditioned by the difference in the polishing performance of the two semiconductor wafers (W1-W4). An Independent claim is included for a polishing method.

    2.
    发明专利
    未知

    公开(公告)号:DE19944304C2

    公开(公告)日:2001-09-20

    申请号:DE19944304

    申请日:1999-09-15

    Abstract: The semiconductor structure has a layer structure formed from a metalization layer and a dielectric layer. The metalization layer is patterned and has contact areas. The dielectric layer is composed of a depositable material and covers the metalization layer. The contact areas are formed from many contiguous individual structures, which are so narrow that the depositable material does not form, over the individual structures, any areas which run parallel to the metalization layer. The grid of contiguous individual structures forms a contact area which causes dielectric layer elevations which are particularly low and therefore easy to planarize.

    7.
    发明专利
    未知

    公开(公告)号:DE10109328A1

    公开(公告)日:2002-09-12

    申请号:DE10109328

    申请日:2001-02-27

    Abstract: The invention relates to a semiconductor substrate (1) on which a first layer (2), a second layer (3) and a third layer (4) are disposed. The third layer (4) is for example a lacquer mask that is used to structure the second layer (3). The second layer (3) is for example a structured hard mask that is used to structure the first layer (2). The third layer (4) is then removed and a fourth layer (8) is deposited. The fourth layer (8) is for example an insulator that fills the trenches formed in the first layer (2). The fourth layer (8) is then planarized in a CMP step, and planarization is continued while the second layer (3) that is for example a hard mask is removed from the first layer (2) together with the fourth layer (8), thereby leaving the fourth layer (8) in a trench (7) that is disposed in the first layer (2).

    Semiconductor structure with multiple metallic layer depositions

    公开(公告)号:DE19944304A1

    公开(公告)日:2001-04-05

    申请号:DE19944304

    申请日:1999-09-15

    Abstract: The semiconductor structure has a layer structure formed from a metallic layer deposition (1) and a dielectric layer (2). The metallic layer deposition is structured and includes contact surface areas (3). The dielectric layer is composed of a removable material and covers the metallic layer deposition. The contact surface areas are formed from many connected single structures (4) which are so narrow, that the removable material forms no surface areas on the single structures, which proceed parallel to the metallic layer deposition. The single structures are preferably narrower than the double thickness, with which the dielectric layer is layered between structures of the metallic layer deposition.

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