公开(公告)号：WO03096412A2

公开(公告)日：2003-11-20

申请号：PCT/EP0305001

申请日：2003-05-13

Applicant: INFINEON TECHNOLOGIES AG ,  DAHL CLAUS ,  MUELLER KARLHEINZ ,  WAGNER CAJETAN

Inventor： DAHL CLAUS ,  MUELLER KARLHEINZ ,  WAGNER CAJETAN

IPC: H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082

CPC classification number: H01L27/0623 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0825

Abstract: In order to integrate an npn bipolar transistor with a hetero bipolar transistor, a placeholder layer is produced (322) in a base area of the hetero bipolar transistor after structuring (320) a collector structure for both types of transistors, wherein the placeholder layer is not present in a base area of the bipolar transistor. The base of the bipolar transistor is covered (326) once the base of the bipolar transistor has been produced (324), whereupon the placeholder layer is removed and the base (328) of the hetero bipolar transistor is then produced on the site from which the placeholder layer has been removed. The emitter structure is then equally produced (330) for both types of transistors so that an integrated circuit comprising the bipolar transistors and the hetero bipolar transistors is obtained, the collector structures and/or the emitter structures of which consist of identical production layers. This makes it possible to produce space-saving and economical integrated circuits profiting from the advantages of both transistor types.

Abstract translation: 用于根据图案化（320）的集电极结构两种晶体管类型的具有异质结双极晶体管的npn双极晶体管的集成是在异质（322），其中所述占位符层不存在于所述双极晶体管的基区的基极区中产生的占位符层。 双极晶体管的基极的生成（324）后，将双极晶体管的基极被覆盖（326），于是在牺牲层被去除，异质结双极型晶体管的基极（328）产生，其中该占位符层已被移除。 其中的发射极结构被同时产生这两种类型的晶体管（330），使得存在一种集成电路，其包括双极晶体管和异质其集电极结构和/或发射器的结构相同的底涂层组成。 因此节省空间和成本效益的集成电路可以由从两种类型的晶体管的优点在于益处。

公开(公告)号：WO0235600A2

公开(公告)日：2002-05-02

申请号：PCT/EP0112035

申请日：2001-10-17

Applicant: INFINEON TECHNOLOGIES AG ,  MUELLER KARLHEINZ ,  WAGNER CAJETAN ,  ROESCHLAU KLAUS

Inventor： MUELLER KARLHEINZ ,  WAGNER CAJETAN ,  ROESCHLAU KLAUS

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/66681 ,  H01L29/42368 ,  H01L29/66674 ,  H01L29/66689

Abstract: The invention relates to a method for producing a DMOS transistor structure. The invention is advantageous in that a protective layer (14) is used to protect the already essentially completed DMOS transistor structure from the negative effects of additional process steps. According to the invention, the DMOS gate electrode is not customarily structured, as in the prior art, by using a single lithography step, rather the structuring of the DMOS gate electrode is split between two lithography steps. In a first lithography step, essentially only the source region (9) of the DMOS transistor structure is opened, whereby the electrode layer still present can be used as a mask for the subsequent production of the body region (8).

Abstract translation: 根据本发明，提供了一种用于制造DMOS晶体管结构的方法。 本发明具有以下优点：使用保护层（14）保护已经基本完成的DMOS晶体管结构免受进一步处理步骤的负面影响。 根据本发明，DMOS栅电极不像现有技术中习惯的那样用单个光刻步骤来图案化，而是将DMOS栅电极的结构分成两个光刻步骤。 在第一光刻步骤中，基本上仅打开DMOS晶体管结构的源极区域（9）。 因此剩余的电极层可以用作随后生产体区（8）的掩模。

公开(公告)号：DE102008001943B4

公开(公告)日：2014-05-15

申请号：DE102008001943

申请日：2008-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： O'RIAIN LINCOLN ,  TILKE ARMIN ,  WAGNER CAJETAN

IPC: H01L21/76 ,  H01L21/74 ,  H01L29/06

Abstract: Halbleiterbauelement, umfassend: ein Halbleitersubstrat oder Werkstück (102), das eine unter einem oberen Abschnitt des Halbleitersubstrats oder Werkstücks angeordnete vergrabene Schicht (104) enthält; eine innerhalb des oberen Abschnitts des Halbleitersubstrats oder Werkstücks (102) angeordnete Isolationsringstruktur (112), die sich vollständig durch mindestens einen Abschnitt der vergrabenen Schicht (104) erstreckt und einen Ring mit einem inneren Gebiet umfasst; und eine innerhalb des inneren Gebiets der Isolationsringstruktur (112) angeordnete diffusionsbeschränkende Struktur (114), gekennzeichnet durch ein leitendes Gebiet (120), das aus dem oberen Abschnitt des Halbleitersubstrats oder Werkstücks (102) innerhalb eines Abschnitts des Inneren der Isolationsringstruktur (112) ausgebildet ist, wobei das leitende Gebiet (120) mindestens ein Dotierstoffelement umfasst, das in den oberen Abschnitt des Halbleitersubstrats oder Werkstücks (102) implantiert und diffundiert ist, wobei die diffusionsbeschränkende Struktur (114) mindestens einen Rand des leitenden Gebiets (120) definiert und wobei das leitende Gebiet an die vergrabene Schicht (104) gekoppelt ist.

公开(公告)号：DE50111707D1

公开(公告)日：2007-02-01

申请号：DE50111707

申请日：2001-10-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER KARLHEINZ ,  WAGNER CAJETAN ,  ROESCHLAU KLAUS

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423

Abstract: A method for the fabrication of a DMOS transistor structure provides the advantage that, through the use of a protective layer, the DMOS transistor structure, which has already been substantially completed, is protected from the adverse effects of further process steps. The DMOS gate electrode is not, as is customary in the prior art, patterned using a single lithography step, but, rather, the patterning of the DMOS gate electrode is split between two lithography steps. In a first lithography step, substantially only the source region of the DMOS transistor structure is opened. Therefore, the electrode layer that is still present can be used as a mask for the subsequent fabrication of the body region.

公开(公告)号：DE10221416A1

公开(公告)日：2003-11-27

申请号：DE10221416

申请日：2002-05-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WAGNER CAJETAN ,  DAHL CLAUS ,  MUELLER KARL-HEINZ

IPC: H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L21/8248

公开(公告)号：DE102008001943A1

公开(公告)日：2009-01-02

申请号：DE102008001943

申请日：2008-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： O'RIAIN LINCOLN ,  TILKE ARMIN ,  WAGNER CAJETAN

IPC: H01L21/76 ,  H01L21/74 ,  H01L29/06

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.

公开(公告)号：AT349074T

公开(公告)日：2007-01-15

申请号：AT01988948

申请日：2001-10-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER KARLHEINZ ,  WAGNER CAJETAN ,  ROESCHLAU KLAUS

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L21/8234

Abstract: A method for the fabrication of a DMOS transistor structure provides the advantage that, through the use of a protective layer, the DMOS transistor structure, which has already been substantially completed, is protected from the adverse effects of further process steps. The DMOS gate electrode is not, as is customary in the prior art, patterned using a single lithography step, but, rather, the patterning of the DMOS gate electrode is split between two lithography steps. In a first lithography step, substantially only the source region of the DMOS transistor structure is opened. Therefore, the electrode layer that is still present can be used as a mask for the subsequent fabrication of the body region.

公开(公告)号：DE102004021240A1

公开(公告)日：2005-11-17

申请号：DE102004021240

申请日：2004-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TILKE ARMIN ,  WAGNER CAJETAN ,  ROCHEL MARKUS

IPC: H01L21/8249 ,  H01L29/737

Abstract: Method and systems for producing a semiconductor circuit arrangement are disclosed. In one implementation, after a formation of a first electrically conductive layer at the surface of a semiconductor substrate for the purpose of realizing a base connection layer and a first split gate layer, an implantation mask is formed for the purpose of carrying out a first collector implantation for the purpose of forming a collector connection zone. After the formation of a hard mask layer and a first etching mask, the hard mask layer is patterned and an emitter window is uncovered using the patterned hard mask layer. Using the patterned hard mask layer a second collector implantation is effected for the purpose of forming a collector zone, a base layer being formed in the region of the emitter window. Afterward, using a second etching mask, a field effect transistor region is uncovered and the patterned hard mask layer is removed in this region in order finally to form a second electrically conductive layer over the whole area for the purpose of realizing an emitter layer and a second split gate layer. Both the bipolar transistor and the field effect transistor are subsequently completed in a customary manner, in particular a source/drain implantation being used simultaneously for the doping of the emitter layer. Since the gate is deposited in two layers, the first layer simultaneously serving as base connection layer and the second layer simultaneously serving as emitter layer, up to two lithography planes can be obviated and costs can thereby be saved.

公开(公告)号：DE10053428A1

公开(公告)日：2002-05-16

申请号：DE10053428

申请日：2000-10-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WAGNER CAJETAN ,  MUELLER KARL-HEINZ ,  ROESCHLAU KLAUS

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/423

Abstract: The invention relates to a method for producing a DMOS transistor structure. The invention is advantageous in that a protective layer (14) is used to protect the already essentially completed DMOS transistor structure from the negative effects of additional process steps. According to the invention, the DMOS gate electrode is not customarily structured, as in the prior art, by using a single lithography step, rather the structuring of the DMOS gate electrode is split between two lithography steps. In a first lithography step, essentially only the source region (9) of the DMOS transistor structure is opened, whereby the electrode layer still present can be used as a mask for the subsequent production of the body region (8).

公开(公告)号：DE102004021240B4

公开(公告)日：2008-07-31

申请号：DE102004021240

申请日：2004-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TILKE ARMIN ,  WAGNER CAJETAN ,  ROCHEL MARKUS

IPC: H01L21/8249 ,  H01L29/737

Abstract: Method and systems for producing a semiconductor circuit arrangement are disclosed. In one implementation, after a formation of a first electrically conductive layer at the surface of a semiconductor substrate for the purpose of realizing a base connection layer and a first split gate layer, an implantation mask is formed for the purpose of carrying out a first collector implantation for the purpose of forming a collector connection zone. After the formation of a hard mask layer and a first etching mask, the hard mask layer is patterned and an emitter window is uncovered using the patterned hard mask layer. Using the patterned hard mask layer a second collector implantation is effected for the purpose of forming a collector zone, a base layer being formed in the region of the emitter window. Afterward, using a second etching mask, a field effect transistor region is uncovered and the patterned hard mask layer is removed in this region in order finally to form a second electrically conductive layer over the whole area for the purpose of realizing an emitter layer and a second split gate layer. Both the bipolar transistor and the field effect transistor are subsequently completed in a customary manner, in particular a source/drain implantation being used simultaneously for the doping of the emitter layer. Since the gate is deposited in two layers, the first layer simultaneously serving as base connection layer and the second layer simultaneously serving as emitter layer, up to two lithography planes can be obviated and costs can thereby be saved.