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1.发明专利Differential current evaluation circuit for evaluating memory state of sram semiconductor memory cell, and sense amplifier circuit 审中-公开用于评估SRAM半导体存储器单元和感测放大器电路的存储状态的差分电流评估电路
公开(公告)号：JP2003323800A
公开(公告)日：2003-11-14
申请号：JP2003127195
申请日：2003-05-02
Applicant: Infineon Technologies Ag , インフィネオン テクノロジーズ アクチエンゲゼルシャフト
Inventor： WICHT BERNHARD , SCHMITT-LANDSIEDEL DORIS , LARGUIER YEAN-YVES
IPC: G11C7/06 , G11C11/413 , G11C11/419 , G11C29/12 , G11C29/00
CPC classification number: G11C11/419 , G11C7/062 , G11C2207/063
Abstract: PROBLEM TO BE SOLVED: To improve circuit structure for reading and evaluating the memory state in a semiconductor memory cell.
SOLUTION: A differential current evaluation circuit (SBS) is provided with input section resistance adjusting means (MIN, MINB) of a differential amplifier (DV) and a current evaluation circuit (SBS). These means (MIN, MINB) are connected to the output parts (outp, outn) and the input parts (inn, inp) of the differential amplifier (DV) and signal lines (BL, BLB), which are electrically connected also to the input parts (inn, inp) of the differential amplifier (DV). A sense amplifier circuit (LV) is provided with a circuit part (ST2). The differential current evaluation circuit (SBS) and the sense amplifier circuit (LV) are arranged in circuit structure for reading and evaluating the memory state of a semiconductor memory cell. A current evaluation circuit is activated, before a reading process and automatically inactivated, immediately after finishing the reading process by a circuit (STAD) for automatic inactivation.
COPYRIGHT: (C)2004,JPOAbstract translation: 要解决的问题：提高用于读取和评估半导体存储单元中的存储器状态的电路结构。 解决方案：差分电流评估电路（SBS）具有差分放大器（DV）和电流评估电路（SBS）的输入部分电阻调节装置（MIN，MINB）。 这些装置（MIN，MINB）连接到差分放大器（DV）和信号线（BL，BLB）的输出部分（outp，outn）和输入部分（inn，inp），它们也电连接到 差分放大器（DV）的输入部分（inn，inp）。 读出放大器电路（LV）具有电路部分（ST2）。 差分电流评估电路（SBS）和读出放大器电路（LV）以电路结构布置，用于读取和评估半导体存储器单元的存储状态。 在读取过程之前，通过电路（STAD）完成读取过程之后立即自动灭活的当前评估电路被自动灭活。 版权所有（C）2004，JPO
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公开(公告)号：DE10041796A1
公开(公告)日：2002-03-14
申请号：DE10041796
申请日：2000-08-25
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WICHT BERNHARD , PAUL STEFFEN
Abstract: An electronic amplifier circuit according to the principle of current detection is coupled to a memory cell field and has an input transistor for each respective row or column of the matrix array. The input transistor is connected to the respective row or column and can be driven and switched by a control signal of a multiplexer circuit. The amplifier circuit may be constructed as a gate circuit or as a transistor diode circuit. A matrix array of memory cells and a matrix array of photodetectors are also provided.
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公开(公告)号：DE102015104946A1
公开(公告)日：2016-10-06
申请号：DE102015104946
申请日：2015-03-31
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHINDLER ALEXIS , ZANNOTH MARKUS , WICHT BERNHARD
IPC: H02M1/08
Abstract: Es werden eine elektronische Treiberschaltung und ein Ansteuerverfahren offenbart. Die Treiberschaltung weist einen Ausgang auf; einen ersten Ausgangstransistor mit einem Steuerknoten und einer Laststrecke, wobei die Laststrecke zwischen den Ausgang und einen ersten Versorgungsknoten geschaltet ist; einen Spannungsregler, der dazu ausgebildet ist, eine Spannung über der Laststrecke des ersten Ausgangstransistors zu steuern; und einen ersten Treiber, der dazu ausgebildet ist, den ersten Ausgangstransistor in Abhängigkeit von einem ersten Steuersignal anzusteuern.
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公开(公告)号：DE10023362A1
公开(公告)日：2001-11-29
申请号：DE10023362
申请日：2000-05-12
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WICHT BERNHARD , PAUL STEFFEN
Abstract: An amplifier circuit configuration includes a data line for transmitting a data signal. The data line is connected to a data signal input of an amplifier by way of a switching device. The amplifier includes a control circuit for controlling an input resistance of the amplifier with a terminal for a control signal. The terminal for the control signal of the control circuit is connected, parallel to the switching device, to the data line. As a consequence, a switching device, which is connected between the data line and the amplifier, has only little influence on the dynamic response when reading out a data signal.
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公开(公告)号：DE10156728A1
公开(公告)日：2003-06-12
申请号：DE10156728
申请日：2001-11-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WICHT BERNHARD , SCHMITT-LANDSIEDEL DORIS
IPC: G11C7/06 , G11C7/12 , G11C11/419 , G11C11/407
Abstract: The memory has several memory cells (SZ1,SZ2), wherein one of the memory cells is read out selectively via a bit line (BL,BLB) and a read amplifier (SA). A regulating circuit (LC) controls the current (IB) of the bit line in dependence on a voltage change of the bit line caused by a leakage current (IL) and compensates the leakage current.
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Patent Agency Ranking
公开(公告)号：DE102015104946B4
公开(公告)日：2021-08-26
申请号：DE102015104946
申请日：2015-03-31
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHINDLER ALEXIS , ZANNOTH MARKUS , WICHT BERNHARD
IPC: H02M1/08
Abstract: Treiberschaltung mit:einem Ausgang (OUT);einem ersten Ausgangstransistor (11) mit einem Steuerknoten (G11) und einer Laststrecke (D11-S11), wobei die Laststrecke (D11-S11) zwischen den Ausgang (OUT) und einen ersten Versorgungsknoten (11) geschaltet ist;einem Spannungsregler (3, 4), der dazu ausgebildet ist, eine Spannung (VDS11) über der Laststrecke des ersten Ausgangstransistors (11) zu regeln, wenn der erste Ausgangstransistor (11) eingeschaltet ist; undeinem ersten Treiber (21), der dazu ausgebildet ist, den ersten Ausgangstransistor (11) in Abhängigkeit von einem ersten Steuersignal (CS11) anzusteuern.
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公开(公告)号：DE10255102B3
公开(公告)日：2004-04-29
申请号：DE10255102
申请日：2002-11-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WICHT BERNHARD , NIRSCHL THOMAS , MARTELLONI YANNICK
IPC: G11C7/02 , G11C11/412 , G11C11/419 , H01L27/11
Abstract: The device is connected to at least one data line and has at least one memory node (K1,K2), at least one selection transistor (M5) connected to the first node, a first data line (BL), a first word line (WL1) and an arrangement (M7) for adapting the leakage current that causes a total leakage current from at least one bit line (BL) into the cell independent of the memory state of the cell, especially in the non-selected state.
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公开(公告)号：DE10219649C1
公开(公告)日：2003-11-27
申请号：DE10219649
申请日：2002-05-02
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WICHT BERNHARD , SCHMITT-LANDSIEDEL DORIS , LARGUIER JEAN-YVES
IPC: G11C7/06 , G11C11/413 , G11C11/419 , G11C29/12
Abstract: The differential electric current evaluation circuit has differential amplifier (DV) with input portions and input resistance adjustment unit with transistors (MIN,MINB). The input portions and output portions of differential amplifier, are connected with signal lines (BL,BLB) with which transistors (MIN,MINB) of input resistance adjustment unit are connected, respectively. Independent claims are also included for the following: (1) sense amplifier circuit; (2) sense amplifier circuit structure.
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公开(公告)号：DE10156728C2
公开(公告)日：2003-11-27
申请号：DE10156728
申请日：2001-11-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WICHT BERNHARD , SCHMITT-LANDSIEDEL DORIS
IPC: G11C7/06 , G11C7/12 , G11C11/419 , G11C11/407
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公开(公告)号：DE10023362C2
公开(公告)日：2002-10-10
申请号：DE10023362
申请日：2000-05-12
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WICHT BERNHARD , PAUL STEFFEN
Abstract: An amplifier circuit configuration includes a data line for transmitting a data signal. The data line is connected to a data signal input of an amplifier by way of a switching device. The amplifier includes a control circuit for controlling an input resistance of the amplifier with a terminal for a control signal. The terminal for the control signal of the control circuit is connected, parallel to the switching device, to the data line. As a consequence, a switching device, which is connected between the data line and the amplifier, has only little influence on the dynamic response when reading out a data signal.
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