公开(公告)号：JP2000353750A

公开(公告)日：2000-12-19

申请号：JP2000144824

申请日：2000-05-17

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BRINTZINGER AXEL ,  KIRIHATA TOSHIAKI ,  NARAYAN CHANDRASEKHAR

IPC: H01L21/82 ,  H01H85/00 ,  H01L23/525 ,  H01H85/044

Abstract: PROBLEM TO BE SOLVED: To array a larger number of fuses densely by electrically connecting at least two fuses that contain a fusing part arrayed in a first level of a multi- layer semiconductor device, respectively. SOLUTION: Each fuse 13 contains a part 15 that is actually fused. The part 15 to be fused is arrayed in a first metal level M1. Like the other part of the fuse 13, the part 15 that is actually fused is made typically of a electrically conductive material, especially aluminum. A termination of each part 15 to be fused is connected to a connector bias 17 that connects that fuse 13 with a connector 19. A gate contact 23 is vertical to a direction of the fuse 13. The gate contact 23 can be connected to a ground that is common to all of existing fuse circuits. Therefore, fuse density is doubled without narrowing the fuse pitch.

公开(公告)号：JP2001068555A

公开(公告)日：2001-03-16

申请号：JP2000210177

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL ,  GABRIEL DANIEL ,  KIRIHATA TOSHIAKI

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02

Abstract: PROBLEM TO BE SOLVED: To combine a laser actuation fuse with an electric starting fuse in order to increase total yield of product. SOLUTION: A plurality of different types of fuses 510, each serving a specified purpose, are arranged on a semiconductor integrated circuit wafer, such that a type of fuse can be actuated without missing the function of different types of fuses. A first type of fuse, e.g. a laser actuation fuse, is principally used for repairing a wafer level defect and a second type of fuse, e.g. an electric starting fuse, is used for repairing a defect found after an IC chip is mounted on a module and a stress is applied to the module during burn-in test. The module level defect is an unit cell trouble corrected normally by an electrically programmed fuse, in order to actuate a module level redundancy arrangement.

公开(公告)号：JP2000311948A

公开(公告)日：2000-11-07

申请号：JP2000092149

申请日：2000-03-29

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ARNDT KENNETH C ,  BRINTZINGER AXEL C ,  CONTI RICHARD A ,  COTE DONNA R ,  NARAYAN CHANDRASEKHAR ,  RAMACHANDRAN RAVIKUMAR ,  RUPP THOMAS S ,  SENTEIRU K SURIINIVUASAN

IPC: H01L21/82 ,  H01H69/02 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for generating a void fuse structure on a gate conductor stack. SOLUTION: A semiconductor substrate is provided, wherein a gate conductor stack 32 is provided on a shallow trench isolation region. Oxide layers 33 and 34 are formed on a substrate around the gate conductor stack 32, and an electric contact opening part etched to the substrate down to the oxide layer is filled with a first conductive material 40, establishing electric contact to the gate conductor stack. A conductive layer 41 of a second conductive material is allowed to stick to the oxide layer and the electric contact, and the oxide layer is anisotropically etched so that at least one etching hole, as far as the shallow trench isolation region through the oxide layer, is formed. A part 60 around the least the etching hole of the oxide layer is isotropically etched to form a void under at least a part of a conductive player pattern. The gate conductor stack comprises a fuse.

公开(公告)号：JP2000243213A

公开(公告)日：2000-09-08

申请号：JP2000046289

申请日：2000-02-23

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： WEBER STEFAN J ,  IGGULDEN ROY ,  NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL CHRISTOPH ,  HOINKIS MARK ,  VAN DEN BERG ROBERT

IPC: H01H85/00 ,  H01H69/02 ,  H01L21/82 ,  H01L23/525

Abstract: PROBLEM TO BE SOLVED: To provide a method for shrinking an area for a fuse to occupy on a semiconductor tip, and to adjust a fuse resistance relative to a fuse of a semiconductor device. SOLUTION: A fuse for a semiconductor is formed, so as to have a substrate 12 having a conductive passage disposed on its surface, a dielectric layer 14 disposed on the substrate, and a vertical fuse 110 vertically disposed on the surface. The vertical fuse penetrates through the dielectric layer 14 and is connected to the conductive passage. The vertical fuse also has a hole 108, a liner material is disposed on its vertical surface, and the fuse is cut off with fusing of the liner material along the vertical surface.

公开(公告)号：WO0163648A9

公开(公告)日：2002-10-24

申请号：PCT/US0105373

申请日：2001-02-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  EINSPRUCH FRED L ,  HAFFNER HENNING ,  THOMAS ALAN C

IPC: H01L23/525 ,  G03F1/14

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion. The second mask portion is of a configuration sufficient to create a latent image of the electrical fuse pattern, including the localized narrowed region of the fuse portion at which the electrical fuse is designed to blow, upon passing the energy beam through the photolithography mask and onto a resist layer. Preferably, the fuse portion of substantially constant width on the determined fuse pattern has a design width less than about 0.25 mu m, and wherein the localized narrowed region of the fuse portion has a design width less than the design width of the fuse portion.

Abstract translation: 制造用于在半导体结构上形成电熔丝的光刻掩模的方法包括：首先确定所需电熔丝的图案，其中所述图案包括基本恒定宽度的熔丝部分，除了熔丝部分的局部变窄区域 电熔丝被设计在其上。 该方法然后包括提供光刻掩模基板，并在光刻掩模基板上产生适于吸收能量束透射的熔丝屏蔽元件。 熔丝掩模元件具有对应于基本恒定宽度的期望电熔丝图案部分的基本恒定宽度的第一掩模部分和对应于熔丝部分的局部变窄区域的第二掩模部分。 第二掩模部分包括与第一掩模部分间隔开的附加掩模元件，第一掩模部分中的窄宽度部分或间隙。 第二掩模部分具有足以产生电熔丝图案的潜像的构造，包括将电熔丝设计成熔断部分的熔断部分的局部变窄区域，以使能量束通过光刻掩模并进入 抗蚀剂层。 优选地，确定的熔丝图案上的基本上恒定的宽度的熔丝部分具有小于约0.25μm的设计宽度，并且其中熔丝部分的局部变窄区域具有小于熔丝部分的设计宽度的设计宽度。

公开(公告)号：WO0163648A3

公开(公告)日：2002-04-18

申请号：PCT/US0105373

申请日：2001-02-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  EINSPRUCH FRED L ,  HAFFNER HENNING ,  THOMAS ALAN C

IPC: H01L23/525 ,  G03F1/14

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion. The second mask portion is of a configuration sufficient to create a latent image of the electrical fuse pattern, including the localized narrowed region of the fuse portion at which the electrical fuse is designed to blow, upon passing the energy beam through the photolithography mask and onto a resist layer. Preferably, the fuse portion of substantially constant width on the determined fuse pattern has a design width less than about 0.25 mu m, and wherein the localized narrowed region of the fuse portion has a design width less than the design width of the fuse portion.

Abstract translation: 制造用于在半导体结构上形成电熔丝的光刻掩模的方法包括：首先确定用于期望的电熔丝的图案，其中该图案包括除了熔丝部分的局部变窄的区域之外基本恒定宽度的熔丝部分 在此电熔丝被设计为吹塑。 该方法然后包括提供光刻掩模衬底并且在光刻掩模衬底上产生适于吸收能量束的透射的熔丝掩模元件。 熔丝掩模元件具有基本恒定宽度的第一掩模部分和与熔丝部分的局部缩窄区域对应的第二掩模部分，第一掩模部分对应于基本恒定宽度的期望电熔丝图案部分。 第二掩模部分包括与第一掩模部分隔开的另外的掩模元件，变窄的宽度部分或第一掩模部分中的间隙。 第二掩模部分具有足以产生电熔丝图案的潜像的配置，该电图案包括保险丝部分的局部变窄的区域，在电熔丝被设计成在该区域处被吹过，在通过能量束通过光刻掩模并且到 抗蚀剂层。 优选地，在所确定的熔丝图案上具有基本恒定宽度的熔丝部分具有小于约0.25μm的设计宽度，并且其中熔丝部分的局部变窄区域具有小于熔丝部分的设计宽度的设计宽度。

公开(公告)号：WO0199148A3

公开(公告)日：2002-08-29

申请号：PCT/US0119240

申请日：2001-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： IYER SUNDAR K ,  BRINTZINGER AXEL ,  SMEYS PETER ,  NARAYAN CHANDRASEKHAR ,  IYER SUBRAMANIAN

IPC: H01L23/525 ,  H01L27/102

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse for semiconductor devices, in accordance with the present invention, includes a cathode (104) including a first dopant type, and an anode (102) including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link (106) connects the cathode and the anode and includes the second dopant type. The fuse link and the cathode form a junction (111) therebetween, and the junction is configured to be reverse biased relative to a cathode potential and an anode potential. A conductive layer (103) is formed across the junction such that current flowing at the junction is diverted into the conductive layer to enhance material migration to program the fuse.

Abstract translation: 根据本发明的用于半导体器件的熔断器包括包括第一掺杂剂型的阴极（104）和包括第二掺杂剂类型的阳极（102），其中第二掺杂剂类型与第一掺杂剂类型相反。 熔丝连接（106）连接阴极和阳极并且包括第二掺杂剂类型。 熔丝链和阴极在其间形成结（111），并且该结被配置为相对于阴极电位和阳极电位被反向偏置。 在结上形成导电层（103），使得在结处流动的电流被转移到导电层中以增强材料迁移以对熔丝进行编程。

公开(公告)号：DE60132435D1

公开(公告)日：2008-03-06

申请号：DE60132435

申请日：2001-03-12

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LARRY ,  HSU LOUIS L ,  NARAYAN CHANDRASEKHAR ,  STEPHENS JEREMY K ,  WISE MICHAEL

IPC: H01L23/525 ,  H01L21/768

Abstract: An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride. The preferred fuse structure comprises an electrically and thermally resistive fuse insulator in the depression, such that the fuse insulator substantially prevents heat of an energy beam directed at the fuse from being transmitted to the semiconductor substrate. More preferably, the fuse formed has a width less that that of the fuse insulator. The fuse structure may further include additional wiring over the electrical insulating layer at the same level as the fuse.

公开(公告)号：HK1035436A1

公开(公告)日：2001-11-23

申请号：HK01104466

申请日：2001-06-28

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BRINTZINGER AXEL ,  KIEWRA EDWARD W ,  NARAYAN CHANDRASEKHAR ,  RADENS CARL J

IPC: H01L21/82 ,  G11C29/04 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/02 ,  H01L27/108 ,  H01L ,  G11C

Abstract: An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.

公开(公告)号：HK1034804A1

公开(公告)日：2001-11-02

申请号：HK01105209

申请日：2001-07-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL ,  DANIEL GABRIEL ,  KIRIHATA TOSHIAKI

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02 ,  H01L

Abstract: A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.