公开(公告)号：US6444548B2

公开(公告)日：2002-09-03

申请号：US25781799

申请日：1999-02-25

Applicant: IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  LI YUJUN ,  MANDELMAN JACK A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108 ,  H01L21/22 ,  H01L21/38 ,  H01L21/425 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10861 ,  H01L21/26586 ,  H01L27/10888 ,  H01L29/66492

Abstract: A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the patterned gate stack, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the patterned gate stack adjacent the bitline contact diffusion region, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the integrated circuit device to drive the halo implant ahead of the impurity.

Abstract translation: 一种用于制造集成电路器件的集成电路器件和方法，包括形成与存储器件相邻的图案化栅叠层，以包括与存储器件相邻的存储节点扩散区域和与存储节点扩散区域相对的位线接触扩散区域， 在存储节点扩散区域和位线接触扩散区域中形成杂质，在图案化的栅极堆叠上形成绝缘体层，从位线接触扩散区域去除绝缘体层的一部分，以沿着图案化的栅极叠层的一部分相邻形成侧壁间隔物 所述位线接触扩散区域将卤素注入物注入到所述位线接触扩散区域中，其中所述绝缘体层不从所述第二扩散区域阻挡所述卤素注入并退火所述集成电路器件以在所述杂质之前驱动所述卤素注入。

公开(公告)号：EP1661176A4

公开(公告)日：2010-03-24

申请号：EP04780833

申请日：2004-08-12

Applicant: IBM

Inventor： WANG GENG ,  MCSTAY KEVIN ,  WEYBRIGHT MARY ELIZABETH ,  LI YUJUN ,  CHIDAMBARRAO DURESETI

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/10

CPC classification number: H01L27/10876 ,  H01L21/26586 ,  H01L27/10864 ,  H01L29/1041 ,  H01L29/66537 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/945

公开(公告)号：WO0193271A2

公开(公告)日：2001-12-06

申请号：PCT/US0117267

申请日：2001-05-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ELLIS WAYNE F ,  LI YUJUN ,  HSU LOUIS L ,  WEINFURTNER OLIVER ,  JI BRIAN L

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4078

CPC classification number: G11C8/08 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4078 ,  G11C2207/104

Abstract: Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.

Abstract translation: 通过使用以一小部分监视晶体管阈值电压跟踪的偏置电压调节来获得改进的晶体管阵列器件性能。 电路和方法对于改善诸如DRAM和嵌入式DRAM的晶体管阵列器件的性能特别有用。 这些优点是特别是当通过至少一个监视晶体管的实际阈值电压的一部分进行跟踪来调节通常提供给阵列的至少两个偏置电压时。 性能改进包括改进的可靠性，更宽的操作偏置条件，降低的功耗以及（在存储器单元的情况下）改进的保留时间。

公开(公告)号：JP2004336049A

公开(公告)日：2004-11-25

申请号：JP2004135830

申请日：2004-04-30

Applicant: Infineon Technol North America Corp ,  Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  インフィニオン テクノロジーズ ノース アメリカ コーポレイション Infineon Technologies North America Corp.

Inventor： BEINTNER JOCHEN ,  LI YUJUN ,  MOUMEN NAIM ,  WRSCHKA PORSHIA SHANE

IPC: H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/665 ,  Y10S438/933

Abstract: PROBLEM TO BE SOLVED: To provide a structure and manufacturing method of a notch gate field effect transistor which can cope with a problem of device (element) reliability.
SOLUTION: A gate dielectric 14 (for example, gate oxide film) is preferably formed on a surface of an active field 10 on a semiconductor substrate defined by a separation trench area 12. Next, a polysilicon layer 16 is accumulated on the gate dielectric. After the above process, a silicon germanium (SiGe) layer 18 is accumulated. Next, a side wall of the polysilicon layer is selectively etched in the transverse direction against the SiGe layer, and a notch gate conductor structure having the SiGe layer wider than the polysilicon layer thereunder is formed. A side wall spacer 26 is formed preferably on the side wall of the SiGe layer and the polysilicon layer. In order to reduce the resistance of a gate conductor 24, preferably, a silicide layer 28 is formed as self-alignment silicide from the polysilicon layer accumulated on the SiGe layer.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：WO0188977A3

公开(公告)日：2002-06-13

申请号：PCT/US0115759

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARARUNI RAMA ,  SRINIVASAN RADHIKA ,  HO HERBERT ,  BEINTNER JOACHEN ,  LI YUJUN ,  LAROSA GIUSEPPE

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/76224

Abstract: A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.

Abstract translation: 提供半导体器件及其制造方法。 在半导体衬底中形成沟槽。 优选在沟槽的表面上形成薄的氧化物衬垫。 氮化物衬垫形成在沟槽中。 电荷被困在氮化物衬垫中。 在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。 优选地，氧化物填充物直接形成在氮化物衬垫上。

公开(公告)号：JP2007053400A

公开(公告)日：2007-03-01

申请号：JP2006289044

申请日：2006-10-24

Applicant: Infineon Technol North America Corp ,  Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  インフィニオン テクノロジーズ ノース アメリカ コーポレイション Infineon Technologies North America Corp.

Inventor： YE QIUYI ,  TONTI WILLIAM R ,  LI YUJUN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/10888 ,  H01L21/76897 ,  H01L27/10894

Abstract: PROBLEM TO BE SOLVED: To provide a dual work function semiconductor structure with borderless contact and a method for manufacturing the same.
SOLUTION: The structure may comprise a substantially cap-free gate 108 and conductive contacts 134 and 170 to a diffusion part 116 adjacent to the cap-free gate, and the conductive contact may include a field effect transistor (FET) borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有无边界接触的双功能半导体结构及其制造方法。 解决方案：该结构可以包括基本无盖的栅极108和导电触点134和170，其连接到与无盖盖栅极相邻的扩散部分116，并且导电触点可以包括无边界的场效应晶体管（FET） 大门。 由于该结构是双重功能结构，所以允许导电接触件在无盖栅极上延伸而不与其电连接。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005175480A

公开(公告)日：2005-06-30

申请号：JP2004353535

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEINTNER JOCHEN C ,  CHIDAMBARRAO DURESETI ,  LI YUJUN ,  SETTLEMYER KENNETH T JR

IPC: H01L21/308 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a FinFET which allows an integrated circuit or an electronic device that includes smaller, more densely disposed active regions or active lines.
SOLUTION: A method of forming an integrated circuit having a FinFET comprises a method of forming sub-lithographic fins. A silicon block is defined by a mask, and a pair of fins which is reduced in width or pulled back by the thickness of one fin on each side is included. After that, a second mask is formed around the first mask so that an aperture having the width of the separation distance between the pair of fins remains in the second mask after the first mask is removed. When the silicon is etched through the aperture, the fins are protected by the second mask, thereby defining the fin thickness by the pullback step.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种FinFET，其允许集成电路或包括更小，更密集布置的有源区或有源线的电子器件。 解决方案：一种形成具有FinFET的集成电路的方法包括形成亚光刻鳍片的方法。 硅块由掩模限定，并且包括在每侧具有一个翅片的宽度减小或拉回的一对翅片。 之后，在第一掩模周围形成第二掩模，使得在去除第一掩模之后，具有一对散热片之间的间隔距离的宽度的孔保持在第二掩模中。 当通过孔蚀刻硅时，翅片被第二掩模保护，从而通过回拉步骤限定翅片厚度。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2002289701A

公开(公告)日：2002-10-04

申请号：JP2002016708

申请日：2002-01-25

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： YE QIUYI ,  TONTI WILLIAM R ,  LI YUJUN

IPC: H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To provide a dual work function semiconductor structure having borderless contact, and to provide a method of fabricating the same. SOLUTION: This structure may include a field effect transistor (FET) having a substantially cap-free gate 108 and conductive contacts 134, 170 to a diffusion 116 adjacent to the cap-free gate, wherein the conductive contacts are borderless to the gate. Because this structure is the dual work function structure, the conductive contacts are allowed to extend over the cap-free gate without being electrically connected thereto.

公开(公告)号：DE60101475D1

公开(公告)日：2004-01-22

申请号：DE60101475

申请日：2001-05-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： ELLIS WAYNE F ,  LI YUJUN ,  HSU L ,  WEINFURTNER OLIVER ,  JI L

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4078

Abstract: Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.

公开(公告)号：DE112004000745B4

公开(公告)日：2008-05-29

申请号：DE112004000745

申请日：2004-05-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  LI YUJUN ,  MOUMEN NAIM ,  WRSCHKA PORSHIA SHANE

IPC: H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.