公开(公告)号：WO0199186A3

公开(公告)日：2002-10-10

申请号：PCT/US0119658

申请日：2001-06-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KUNKEL GERHARD ,  KOTECKI DAVID ,  PARK YOUNG JIN ,  GUTMANN ALOIS ,  MANDELMAN JACK A

IPC: H01L21/761 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/761

Abstract: A semiconductor device, in accordance with the present invention, includes a doped semiconductor substrate (102) wherein the doping of the substrate has a first conductivity and a device region (110) formed near a surface of the substrate. The device region includes at least one device well. A buried well (104) is formed in the substrate below the device region. The buried well is doped with dopants having a second conductivity. A trench region (124) surrounds the device region and extends below the surface of the substrate to at least the buried well such that the device region is isolated from other portions of the substrate by the buried well and the trench region.

Abstract translation: 根据本发明的半导体器件包括其中衬底的掺杂具有第一导电性的掺杂半导体衬底（102）和形成在衬底的表面附近的器件区（110）。 器件区域包括至少一个器件。 掩埋阱（104）形成在器件区域下方的衬底中。 掩埋阱掺杂具有第二导电性的掺杂剂。 沟槽区域（124）围绕器件区域并且在衬底的表面下方延伸到至少掩埋阱，使得器件区域通过掩埋阱和沟槽区域与衬底的其他部分隔离。

公开(公告)号：WO0203423A8

公开(公告)日：2002-04-11

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532 ,  H01L

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts because the stacked capacitors are co-planar with the bit lines and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供DRAM单元和制造方法，其通过将堆叠的电容器结构与电触点合并来消除关键的光刻制造步骤。 因为堆叠的电容器与位线共面并且堆叠的电容器位于位线之间提供的绝缘材料中，所以可以使用单个光刻步骤来形成电触点。 与传统的电容器位线（COB）DRAM单元不同，这种位于电容器旁边的位线DRAM单元消除了对电容器专用接触的需要，使得可以用较低的全局地形实现更高的电容。

公开(公告)号：WO0225730A3

公开(公告)日：2002-10-24

申请号：PCT/US0142263

申请日：2001-09-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  DIVAKARUNI RAMACHANDRAN ,  REITH ARMIN M ,  NAEEM MUNIR D

IPC: H01L21/8242

CPC classification number: H01L27/10864 ,  H01L27/1087 ,  H01L27/10891

Abstract: A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) (104) is formed over a semiconductor region (e.g., a silicon substrate) (100). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) (112, 120) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench (122) can be etched in the semiconductor region. The trench would be substantially aligned to the second material.

Abstract translation: 可以在制造动态随机存取存储器（DRAM）单元中使用形成沟槽的方法。 在一个方面，第一材料（例如，多晶硅）（104）的第一层形成在半导体区域（例如，硅衬底）（100）之上。 第一层被图案化以去除第一材料的一部分。 然后可以沉积第二材料（例如氧化物）（112,120）以填充第一材料被去除的部分。 在去除第一层第一材料的剩余部分之后，可以在半导体区中蚀刻沟槽（122）。 沟槽将基本上与第二材料对齐。

公开(公告)号：WO0201293A3

公开(公告)日：2002-08-15

申请号：PCT/US0120408

申请日：2001-06-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SEITZ MIHEL ,  KUNKEL GERHARD

IPC: G03F1/00 ,  G03F1/14

CPC classification number: G03F1/36

Abstract: A photomask for lithographic processing, in accordance with the present invention, includes a plurality of features (104) for providing an image pattern. The features are arranged in a column (106) on a mask substrate (101). Each feature is dimensioned to provide an individual image separate from all other images provided by the photomask when exposed to light. A line feature (110) is formed on the mask substrate and extends between and intersects with each of the plurality of features in the column. The line feature extends a length of images produced by the plurality of features arranged in the column when exposed to light wherein the images produced by each of the plurality of features and the line feature remain separate from each other.

Abstract translation: 根据本发明的用于光刻处理的光掩模包括用于提供图像图案的多个特征（104）。 这些特征被布置在掩模衬底（101）上的列（106）中。 每个特征的尺寸被设计成提供与暴露于光线时由光掩模提供的所有其他图像分离的单独图像。 线特征（110）形成在掩模基板上并且在列中的多个特征中的每个特征之间延伸并与之交叉。 当暴露于光线时，线条特征延伸由排列在列中的多个特征产生的图像的长度，其中由多个特征中的每一个和线条特征产生的图像保持彼此分离。

公开(公告)号：WO0225730A8

公开(公告)日：2002-12-27

申请号：PCT/US0142263

申请日：2001-09-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  DIVAKARUNI RAMACHANDRAN ,  REITH ARMIN M ,  NAEEM MUNIR D

IPC: H01L21/8242

CPC classification number: H01L27/10864 ,  H01L27/1087 ,  H01L27/10891

Abstract: A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) (104) is formed over a semiconductor region (e.g., a silicon substrate) (100). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) (112, 120) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench (122) can be etched in the semiconductor region. The trench would be substantially aligned to the second material.

Abstract translation: 形成沟槽的方法可用于制造动态随机存取存储器（DRAM）单元。 在一个方面，在半导体区域（例如，硅衬底）（100）上形成第一材料（例如，多晶硅）（104）的第一层。 图案化第一层以去除第一材料的部分。 然后可以沉积第二材料（例如氧化物）（112,120）以填充去除第一材料的部分。 在去除第一材料的第一层的剩余部分之后，可以在半导体区域中蚀刻沟槽（122）。 沟槽将基本上对准第二材料。

公开(公告)号：WO0199150A2

公开(公告)日：2001-12-27

申请号：PCT/US0119679

申请日：2001-06-20

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： YIN XIAOMING ,  GOULD CHRISTOPHER ,  KUNKEL GERHARD

IPC: G03F7/20 ,  H01L

CPC classification number: G03F7/70633

Abstract: In an overlay measurement mark comprising an inner box (2) and an outer box (4) located at a predetermined area on a mask through which patterns are formed on a semiconductor device, the improvement of an overlay mark that extends the overlay measurement range comprising: in-focused marks means printed at an optimal or ideal focal plane level from an illumination source, and de-focused marks means located at a different focus level from the optimal focal plane to provide image placement shift of the de-focused marks larger than that of the in-focused marks means to enable measurement of the shift of de-focused marks that are not attributable to a mechanical alignment error to be determined with greater accuracy.

Abstract translation: 在包括位于掩模上的预定区域上的内盒（2）和外箱（4）的覆盖测量标记中，通过图案形成在半导体器件上的预定区域，覆盖标记的改进扩展了重叠测量范围，包括 ：聚焦内标记意味着以最佳或理想的焦平面级别从照明源打印，并且解聚焦标记装置位于与最佳焦平面不同的聚焦水平上，以提供大于 被聚焦的标记的意思是使得能够以更高的精度确定不归因于机械对准误差的去焦点标记的偏移的测量。

公开(公告)号：WO0203423A3

公开(公告)日：2002-08-08

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts (28) because the stacked capacitors (46,48,50) are co-planar with the bit lines (36) and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供了一种DRAM单元和制造方法，其通过将堆叠的电容器形成与电触点并入来消除关键的光刻制造步骤。 由于层叠的电容器（46,48,50）与位线（36）是共面的，所以单个光刻步骤可用于形成电触点（28），并且堆叠的电容器位于设置在 位线。 与常规的电容器位线（COB）DRAM单元不同，这种位线旁边的DRAM电池消除了将触点专用于电容器的需要，使得可以在较低的全局地形下实现更高的电容。

公开(公告)号：WO0201568A3

公开(公告)日：2002-06-06

申请号：PCT/US0120406

申请日：2001-06-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： KUNKEL GERHARD ,  BUTT SHAHID

IPC: G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/409

CPC classification number: H01L27/10882 ,  G11C11/4097 ,  H01L27/10841

Abstract: A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active area where the two crossbars intersect serves as the common base region of the four transistors of the cluster. The top of the base region serves as a common drain for the four transistors and each transistor has a separate channel along the wall of its associated vertical trench that provides its storage capacitor. Each cluster includes a common bit line and four separate word-line contacts.

Abstract translation: 动态随机存取存储器形成在簇的阵列中的硅芯片中，四个单元中的每一个在单个有效区域中。 每个活动区域在两根横杆的四端带有垂直沟槽的十字形。 两个横杆相交的有效区域的中心区域用作该群集的四个晶体管的公共基极区域。 基极区域的顶部用作四个晶体管的公共漏极，并且每个晶体管沿着其提供其存储电容器的相关垂直沟槽的壁具有单独的沟道。 每个群集包括一个公共位线和四个单独的字线接触。

公开(公告)号：WO0184235A2

公开(公告)日：2001-11-08

申请号：PCT/US0111696

申请日：2001-04-10

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： BUKOFSKY SCOTT J ,  KUNKEL GERHARD ,  WISE RICHARD ,  WONG ALFRED

IPC: G03F1/00 ,  G03F7/20 ,  G03F

CPC classification number: G03F7/70466 ,  G03F7/203

Abstract: A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the reticle mask by removing a set(s) of the features that are juxtaposed to form hollow polygonally-shaped clusters with a gap in the center. Form unexposed resist on the workpiece. Load the workpiece and the reticle mask into the stepper. Expose the workpiece through the reticle mask. Reposition the workpiece by a nanostep. Then expose the workpiece through the reticle mask after the repositioning. Test whether the plural exposure process is finished. If the result of the test is NO the process loops back to repeat some of the above steps. Otherwise the process has been completed. An overlay mark is produced by plural exposures of a single mark. A dead zone is provided surrounding an array region in which printing occurs subsequent to exposure in an original exposure. Alternatively, the workpiece can be fully exposed first by stepping a series of full steps, then going back to the starting position, making a nanostep to reset the starting position and re-exposing from the reset starting position in the same way with full steps from the nanostepped position. The clusters may be in the shape of a hexagon or a diamond.

Abstract translation: 用于在双重曝光步骤和重复过程中曝光工件的方法通过形成掩模版掩模的设计而开始。 通过移除一些并列的特征来形成掩模版掩模的设计，以形成具有中心间隙的中空多边形簇。 在工件上形成未曝光的抗蚀剂。 将工件和掩模版掩模装入步进器。 通过掩模掩模将工件暴露。 用纳秒级重新定位工件。 然后在重新定位后将工件暴露在掩模版掩模之外。 测试多次曝光过程是否完成。 如果测试结果为“否”，则过程循环返回以重复上述步骤。 否则该过程已经完成。 通过单个标记的多次曝光产生重叠标记。 围绕阵列区域提供死区，其中在原始曝光中曝光之后发生印刷。 或者，可以通过步进一系列完整的步骤，然后返回到起始位置，首先完全暴露工件，从而使得纳秒能够以相同的方式从复位起始位置复位起始位置并再次曝光 纳米级位置。 簇可以是六边形或菱形的形状。

公开(公告)号：DE10207817A1

公开(公告)日：2003-05-28

申请号：DE10207817

申请日：2002-02-25

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： GENZ OLIVER ,  PREUNINGER JUERGEN ,  KUNKEL GERHARD

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/8242

Abstract: An apparatus (100) for patterning the surface of a semiconductor wafer (130). A stage (148) is coupled to a motor (150) that is adapted to move the stage (148) and a semiconductor wafer (130) in a horizontal direction at a first speed A. A mask (140) is disposed above the semiconductor wafer (130), the mask (140) being coupled to a motor (142) that is adapted to move the mask (140) in a horizontal direction at a second speed B. The ratio of the first and second speeds is different than the magnification factor, which may be other than 1:1 if a lens (120) is used. The mask (140) and the wafer (130) may be moved in the same horizontal direction simultaneously during the exposure process at different speeds B and A, respectively, to provide a magnification or demagnification of the mask (140) pattern onto the wafer (130) surface.