公开(公告)号：US09385212B2

公开(公告)日：2016-07-05

申请号：US14725666

申请日：2015-05-29

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Guilei Wang ,  Huilong Zhu

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; epitaxially growing raised source/drain regions on the top of the fins on opposite sides of the gate spacer in the first direction; performing lightly-doping ion implantation through the raised source/drain regions with the gate spacer as a mask, to form source/drain extension regions in the fins on opposite sides of the gate spacer in the first direction; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在基板上形成沿第一方向延伸的多个翅片; 在翅片上形成沿着第二方向延伸的虚拟栅极堆叠; 在第一方向上在虚拟栅极堆叠的相对侧上形成栅极间隔物; 在第一方向上在栅极间隔物的相对侧的翅片的顶部外延生长凸起的源极/漏极区域; 通过栅极间隔物作为掩模，通过凸起的源极/漏极区进行轻掺杂离子注入，以在第一方向上在栅极间隔物的相对侧的鳍中形成源极/漏极延伸区域; 去除虚拟栅极堆叠以形成栅极沟槽; 以及在栅极沟槽中形成栅叠层。

公开(公告)号：US20150228480A1

公开(公告)日：2015-08-13

申请号：US14688788

申请日：2015-04-16

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Changliang Qin ,  Zuozhen Fu ,  Xiaolong Ma ,  Dapeng Chen

IPC: H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/02603 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

Abstract translation: 公开了堆叠的纳米线MOS晶体管的制造方法。 一方面，该方法包括在基板上沿着第一方向形成多个散热片。 该方法还包括在每个翅片中形成由多个纳米线构成的纳米线堆叠。 该方法还包括在纳米线堆叠中沿着第二方向形成栅极堆叠，所述栅极堆叠围绕纳米线堆叠。 该方法还包括在栅极堆叠的两侧形成源极/漏极区域，构成沟道区域的各个源极/漏极区域之间的纳米线。 可以通过多次蚀刻形成一叠纳米线，横向蚀刻沟槽并填充沟槽。 横向蚀刻工艺包括具有内部切线和横向蚀刻的各向同性干法蚀刻，以及沿相应晶体学方向选择性蚀刻的湿蚀刻。

公开(公告)号：US09865686B2

公开(公告)日：2018-01-09

申请号：US14646583

申请日：2013-08-12

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Huilong Zhu ,  Xiaolong Ma

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L21/306 ,  H01L21/308 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L21/28 ,  H01L29/267 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a fin extending on a substrate along a first direction; a gate extending along a second direction across the fin; and source/drain regions and a gate spacer on the fin at opposite sides of the gate, in which there is a surface layer on the top and/or sidewalls of the fin.

公开(公告)号：US09892912B2

公开(公告)日：2018-02-13

申请号：US14688788

申请日：2015-04-16

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Changliang Qin ,  Zuozhen Fu ,  Xiaolong Ma ,  Dapeng Chen

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/00 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L21/02603 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

公开(公告)号：US09391073B2

公开(公告)日：2016-07-12

申请号：US14397822

申请日：2013-08-06

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang Yin ,  Xiaolong Ma ,  Weijia Xu ,  Qiuxia Xu ,  Huilong Zhu

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: A FinFET device and a method for manufacturing the same. The FinFET device includes a plurality of fins each extending in a first direction on a substrate; a plurality of gate stacks each being disposed astride the plurality of fins and extending in a second direction; a plurality of source/drain region pairs, respective source/drain regions of each source/drain region pair being disposed on opposite sides of the each gate stack in the second direction; and a plurality of channel regions each comprising a portion of a corresponding fin between the respective source/drain regions of a corresponding source/drain pair, wherein the each fin comprises a plurality of protruding cells on opposite side surfaces in the second direction.

Abstract translation: FinFET器件及其制造方法。 FinFET器件包括多个翅片，每个翅片沿基底上的第一方向延伸; 多个栅极堆叠，每个栅极叠堆叠跨越所述多个散热片并沿第二方向延伸; 多个源/漏区对，每个源极/漏极区对的各个源极/漏极区在第二方向上设置在每个栅极堆叠的相对侧上; 以及多个通道区域，每个沟道区域包括在相应的源极/漏极对的各个源极/漏极区域之间的相应鳍片的一部分，其中每个鳍片包括在第二方向的相对侧表面上的多个突起单元。

公开(公告)号：US20160071952A1

公开(公告)日：2016-03-10

申请号：US14725666

申请日：2015-05-29

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Guilei Wang ,  Huilong Zhu

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; epitaxially growing raised source/drain regions on the top of the fins on opposite sides of the gate spacer in the first direction; performing lightly-doping ion implantation through the raised source/drain regions with the gate spacer as a mask, to form source/drain extension regions in the fins on opposite sides of the gate spacer in the first direction; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在基板上形成沿第一方向延伸的多个翅片; 在翅片上形成沿着第二方向延伸的虚拟栅极堆叠; 在第一方向上在虚拟栅极堆叠的相对侧上形成栅极间隔物; 在第一方向上在栅极间隔物的相对侧的翅片的顶部外延生长凸起的源极/漏极区域; 通过栅极间隔物作为掩模，通过凸起的源极/漏极区进行轻掺杂离子注入，以在第一方向上在栅极间隔物的相对侧的鳍中形成源极/漏极延伸区域; 去除虚拟栅极堆叠以形成栅极沟槽; 以及在栅极沟槽中形成栅叠层。

公开(公告)号：US08936988B2

公开(公告)日：2015-01-20

申请号：US14266521

申请日：2014-04-30

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Qingqing Liang ,  Xiaolong Ma

IPC: H01L21/336 ,  H01L21/31 ,  H01L29/78

CPC classification number: H01L29/7847 ,  H01L21/02115 ,  H01L21/02266 ,  H01L21/02274 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/7849

Abstract: A method for manufacturing a semiconductor device is disclosed. In one aspect the method includes forming a gate stack over a substrate. The method also includes forming a dummy sidewall spacer around the gate stack. The method also includes depositing a stress liner of diamond-like amorphous carbon (DLC) on the substrate, the gate stack and the dummy sidewall spacer. The method also includes annealing, so that a channel region in the substrate below the gate stack and the gate stack memorize stress in the stress liner. The method also includes removing the dummy sidewall spacer. The method also includes forming a sidewall spacer around the gate stack. In the method according to the disclosed technology, large stress in the liner of DLC is memorized and applied to the dummy gate stack and the channel region.

Abstract translation: 公开了一种制造半导体器件的方法。 在一个方面，该方法包括在衬底上形成栅叠层。 该方法还包括在栅极叠层周围形成虚设的侧壁间隔物。 该方法还包括在衬底上，沉积金刚石状无定形碳（DLC）的应力衬垫，栅极堆叠和虚设侧壁间隔物。 该方法还包括退火，使得栅极堆叠下方的衬底中的沟道区域和栅极堆叠在应力衬垫中记忆应力。 该方法还包括去除虚拟侧壁间隔物。 该方法还包括在栅叠层周围形成侧墙。 在根据所公开的技术的方法中，DLC的衬垫中的大应力被存储并应用于虚拟栅极堆叠和沟道区域。

公开(公告)号：US20140256109A1

公开(公告)日：2014-09-11

申请号：US14266521

申请日：2014-04-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang Yin ,  Qingqing Liang ,  Xiaolong Ma

IPC: H01L29/78

CPC classification number: H01L29/7847 ,  H01L21/02115 ,  H01L21/02266 ,  H01L21/02274 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/7849

Abstract: A method for manufacturing a semiconductor device is disclosed. In one aspect the method includes forming a gate stack over a substrate. The method also includes forming a dummy sidewall spacer around the gate stack. The method also includes depositing a stress liner of diamond-like amorphous carbon (DLC) on the substrate, the gate stack and the dummy sidewall spacer. The method also includes annealing, so that a channel region in the substrate below the gate stack and the gate stack memorize stress in the stress liner. The method also includes removing the dummy sidewall spacer. The method also includes forming a sidewall spacer around the gate stack. In the method according to the disclosed technology, large stress in the liner of DLC is memorized and applied to the dummy gate stack and the channel region to increase carrier mobility and improve performances of the device.

Abstract translation: 公开了一种制造半导体器件的方法。 在一个方面，该方法包括在衬底上形成栅叠层。 该方法还包括在栅极叠层周围形成虚设的侧壁间隔物。 该方法还包括在衬底上，沉积金刚石状无定形碳（DLC）的应力衬垫，栅极堆叠和虚设侧壁间隔物。 该方法还包括退火，使得栅极堆叠下方的衬底中的沟道区域和栅极堆叠在应力衬垫中记忆应力。 该方法还包括去除虚拟侧壁间隔物。 该方法还包括在栅叠层周围形成侧墙。 在根据所公开的技术的方法中，DLC的衬垫中的大应力被存储并应用于虚拟栅极堆叠和沟道区域以增加载流子迁移率并提高器件的性能。

公开(公告)号：US20140217362A1

公开(公告)日：2014-08-07

申请号：US13812503

申请日：2012-10-12

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/15 ,  B82Y10/00 ,  H01L29/1054 ,  H01L29/151 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/7781 ,  H01L29/785 ,  H01L29/7853

Abstract: The present invention discloses a method for manufacturing a semiconductor device, which comprises: forming a plurality of fins on a substrate, which extend along a first direction and have rhombus-like cross-sections; forming a gate stack structure on each fin, which traverses the plurality of fins and extends along a second direction; wherein a portion in each fin that is under the gate stack structure forms a channel region of the device, and portions in each fin that are at both sides of the gate stack structure along the first direction form source and drain regions. The semiconductor device and its manufacturing method according to the present invention use rhombus-like fins to improve the gate control capability to effectively suppress the short channel effect, moreover, an epitaxial quantum well is used therein to better limit the carriers, thus improving the device drive capability.

Abstract translation: 本发明公开了一种半导体器件的制造方法，其特征在于，在基板上形成沿着第一方向延伸并具有菱形状的横截面的多个翅片， 在每个翅片上形成栅极堆叠结构，其横过所述多个翅片并沿着第二方向延伸; 其中位于所述栅极堆叠结构下方的每个鳍中的部分形成所述器件的沟道区，并且沿着所述第一方向位于所述栅极堆叠结构两侧的每个鳍中的部分形成源极和漏极区。 根据本发明的半导体器件及其制造方法使用菱形翅片来提高栅极控制能力以有效地抑制短沟道效应，此外，在其中使用外延量子阱以更好地限制载流子，从而改善器件 驱动能力。

公开(公告)号：US20140054658A1

公开(公告)日：2014-02-27

申请号：US13812499

申请日：2012-10-12

Applicant: THE INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

IPC: H01L29/66 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/66477 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02675 ,  H01L21/26506 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7848

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least one of the source and drain regions comprises a GeSn alloy. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn stressed source and drain regions with high concentration of Sn is formed by implanting precursors and performing a laser rapid annealing, thus the device carrier mobility of the channel region is effectively enhanced and the device drive capability is further improved.

Abstract translation: 本发明公开了一种半导体器件，包括：衬底，衬底上的栅极堆叠结构，栅极堆叠结构两侧的衬底中的源极和漏极区域以及衬底中的源极和漏极区域之间的沟道区域 其特征在于源区和漏区中的至少一个包括GeSn合金。 根据本发明的半导体器件及其制造方法，通过注入前体并进行激光快速退火形成GeSn应力的高浓度Sn的源区和漏极区，因此沟道区的器件载流子迁移率为 有效提高了设备​​驱动能力。