公开(公告)号：WO2014107143A3

公开(公告)日：2014-09-25

申请号：PCT/US2012059204

申请日：2012-10-08

Applicant: INTEL CORP ,  LEWIS BRIAN T ,  SAHA BRATIN

Inventor： LEWIS BRIAN T ,  SAHA BRATIN

IPC: G06F9/46

CPC classification number: G06F9/4843 ,  G06F9/467 ,  G06F9/4881

Abstract: An apparatus and method is described herein for adaptive thread scheduling in a transactional memory environment. A number of conflicts in a thread over time are tracked. And if the conflicts exceed a threshold, the thread may be delayed (adaptively scheduled) to avoid conflicts between competing threads. Moreover, a more complex version may track a number of transaction aborts within a first thread that are caused by a second thread over a period, as well as a total number of transactions executed by the first thread over the period. From the tracking, a conflict ratio is determined for the first thread with regard to the second thread. And when the first thread is to be scheduled, it may be delayed if the second thread is running and the conflict ratio is over a conflict ratio threshold.

Abstract translation: 这里描述了一种在事务存储器环境中的自适应线程调度的装置和方法。 跟踪线程中的一些冲突。 并且如果冲突超过阈值，线程可能被延迟（自适应调度），以避免竞争线程之间的冲突。 此外，更复杂的版本可以跟踪在一段时间内由第二线程引起的第一线程内的多个事务中止以及在该周期上由第一线程执行的事务的总数。 从跟踪中，针对第二线程确定第一线程的冲突比。 并且当第一个线程被调度时，如果第二个线程正在运行并且冲突比超过了冲突比阈值，它可能被延迟。

公开(公告)号：SG11201704042PA

公开(公告)日：2017-07-28

申请号：SG11201704042P

申请日：2015-11-24

Applicant: INTEL CORP

Inventor： LEWIS BRIAN T ,  BARIK RAJKISHORE ,  SHPEISMAN TATIANA

IPC: G06F13/12 ,  G06F13/16

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.

公开(公告)号：EP2775982A4

公开(公告)日：2016-04-20

申请号：EP12887860

申请日：2012-10-08

Applicant: INTEL CORP

Inventor： LEWIS BRIAN T ,  SAHA BRATIN

IPC: G06F9/46 ,  G06F9/48

CPC classification number: G06F9/4843 ,  G06F9/467 ,  G06F9/4881

公开(公告)号：EP3234785A4

公开(公告)日：2018-05-30

申请号：EP15870620

申请日：2015-11-24

Applicant: INTEL CORP

Inventor： LEWIS BRIAN T ,  BARIK RAJKISHORE ,  SHPEISMAN TATIANA

IPC: G06F13/12 ,  G06F13/16

CPC classification number: G06F9/544 ,  G06T1/20

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.

公开(公告)号：EP3053026A4

公开(公告)日：2017-04-12

申请号：EP13895086

申请日：2013-10-04

Applicant: INTEL CORP

Inventor： BARIK RAJKISHORE ,  LEWIS BRIAN T ,  SHPEISMAN TATIANA

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/50

CPC classification number: G06F9/30145 ,  G06F1/263 ,  G06F8/451 ,  G06F9/3822 ,  G06F9/5094 ,  G06F2209/508 ,  Y02D10/22

Abstract: Various embodiments are generally directed to techniques for assigning instances of blocks of instructions of a routine to one of multiple types of core of a heterogeneous set of cores of a processor component. An apparatus to select types of cores includes a processor component; a core selection component for execution by the processor component to select a core of multiple cores to execute an initial subset of multiple instances of an instruction block in parallel based on characteristics of instructions of the instruction block, and to select a core of the multiple cores to execute remaining instances of the multiple instances of the instruction block in parallel based on characteristics of execution of the initial subset stored in an execution database; and a monitoring component for execution by the processor component to record the characteristics of execution of the initial subset in the execution database. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常涉及将例程的指令块的实例分配给处理器组件的异构核心集合的多种类型的核心之一的技术。 选择核心类型的装置包括处理器组件; 核心选择部件，用于由处理器部件执行以选择多个核的核心，以基于指令块的指令的特性并行地执行指令块的多个实例的初始子集，并且选择多个核心的核心 基于存储在执行数据库中的初始子集的执行特性并行执行指令块的多个实例的剩余实例; 以及用于由处理器组件执行以在执行数据库中记录初始子集的执行特性的监视组件。 描述和要求保护其他实施例。

公开(公告)号：DE102018110380A1

公开(公告)日：2018-10-31

申请号：DE102018110380

申请日：2018-04-30

Applicant: INTEL CORP

Inventor： BARIK RAJKISHORE ,  LEWIS BRIAN T ,  SUNDARESAN MURALI ,  JACKSON JEFFREY ,  MACPHERSON MIKE ,  CHEN XIAOMING

IPC: G06F9/50

Abstract: Beschrieben ist ein Mechanismus zur Ermöglichung der intelligenten Ressourcenverteilung zum Tiefenlernen bei autonomen Maschinen.. Ein Verfahren von Ausführungsformen, wie hierin beschrieben, beinhaltet das Erkennen eines oder mehrerer Sätze von Daten aus einer oder mehreren Quellen über eines oder mehrere Netzwerke, und das Einfügen einer Bibliothek in eine neuronale Netzwerkanwendung, um den optimalen Punkt zu bestimmen, an dem die Frequenzskalierung anzuwenden ist, ohne die Leistung der neuronalen Netzwerkanwendung an einer Rechenvorrichtung zu beeinträchtigen.

公开(公告)号：DE102018110369A1

公开(公告)日：2018-10-31

申请号：DE102018110369

申请日：2018-04-30

Applicant: INTEL CORP

Inventor： LEWIS BRIAN T ,  CHEN FENG ,  JACKSON JEFFREY R ,  GOTTSCHLICH JUSTIN E ,  BARIK RAJKISHORE ,  CHEN XIAOMING ,  SURTI PRASOONKUMAR ,  SUNDARESAN MURALI ,  MACPHERSON MIKE B

IPC: G06F9/50

Abstract: Beschrieben ist ein Mechanismus zur Ermöglichung einer intelligenten Sammlung von Daten und zur intelligenten Verwaltung von autonomen Maschinen. Ein Verfahren von Ausführungsformen, wie hierin beschrieben, beinhaltet das Erkennen eines oder mehrerer Sätze von Daten von einer oder mehreren Quellen über ein oder mehrere Netzwerke, und das Kombinieren einer ersten Berechnung, die lokal an einer lokalen Rechenvorrichtung ausgeführt wird, mit einer zweiten Berechnung, die entfernt an einer entfernten Rechenvorrichtung in Kommunikation mit der lokalen Rechenvorrichtung über das eine oder die mehreren Netzwerke ausgeführt wird, wobei die erste Berechnung wenig Energie verbraucht, wobei die zweite Berechnung viel Energie verbraucht.