中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.021 seconds)

    Mechanism to schedule thread on os-sequestered sequencer without operating system intervention
    1.
    发明专利
    Mechanism to schedule thread on os-sequestered sequencer without operating system intervention 审中-公开
    在没有操作系统干预的情况下在OS-序列测序仪上安排螺线的机制

    公开(公告)号：JP2011076639A

    公开(公告)日：2011-04-14

    申请号：JP2011007496

    申请日：2011-01-18

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： BIGBEE BRYANT ,  HANKINS RICHARD A ,  WANG HONG ,  DIEP TRUNG ,  XINMIN TIAN ,  KAUSHIK CHIV ,  SHEN JOHN ,  MALLICK ASIT ,  GIRKAR MILLIND ,  SETHI PRASHANT ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  HELD JAMES PAUL

    IPC: G06F9/46

    CPC classification number: G06F9/4843

    Abstract: PROBLEM TO BE SOLVED: To provide a method, apparatus and system for scheduling OS-independent 'shreds' without intervention of an operating system.
    SOLUTION: For at least in one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. The scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于在不介入操作系统的情况下调度与OS无关的“碎片”的方法，装置和系统。 解决方案：至少在一个实施例中，碎片被调度为由调度器例程而不是操作系统执行。 调度程序例程可以在每个启用的定序器上运行。 调度器可以从队列系统检索碎片描述符。 与调度器相关联的定序器然后可以执行由描述符描述的碎片。 还描述和要求保护其他实施例。 版权所有（C）2011，JPO＆INPIT

    Mechanism for scheduling thread on os isolated sequencer without interposition of operating system
    2.
    发明专利
    Mechanism for scheduling thread on os isolated sequencer without interposition of operating system 有权
    用于在没有操作系统中断的操作系统分离序列上安排螺纹的机构

    公开(公告)号：JP2013191244A

    公开(公告)日：2013-09-26

    申请号：JP2013140714

    申请日：2013-07-04

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： BIGBEE BRYANT ,  HANKINS RICHARD A ,  WANG HONG ,  DIEP TRUNG ,  XINMIN TIAN ,  KAUSHIK CHIV ,  JOHN SHEN ,  MALLICK ASIT ,  GIRKAR MILLIND ,  SETHI PRASHANT ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  HELD JAMES PAUL

    IPC: G06F9/46

    CPC classification number: G06F9/4843

    Abstract: PROBLEM TO BE SOLVED: To provide various embodiments of a method, a device and a system for scheduling OS independent 'shred' without interposition of an operating system.SOLUTION: For at least one embodiment, a shred is scheduled for execution not by an operating system but by a scheduler routine. The scheduler routine can travel on the respective validated sequencers. A scheduler can acquire a shred descriptor from a queue system. Next, a sequencer associated with the scheduler can execute the shred to be described by the descriptor. Other embodiments are also described, and claimed.

    Abstract translation: 要解决的问题：提供方法，设备和系统的各种实施例，用于在不插入操作系统的情况下调度独立于OS的“独立”操作系统。解决方案：对于至少一个实施例，碎片被安排执行而不是通过操作 系统，但通过调度程序。 调度程序可以在相应的经过验证的定序器上运行。 调度程序可以从队列系统中获取碎片描述符。 接下来，与调度器相关联的定序器可以执行由描述符描述的细丝。 还描述和要求保护其他实施例。

    Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory
    5.
    发明专利
    Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory 未知

    公开(公告)号：GB2506788A

    公开(公告)日：2014-04-09

    申请号：GB201400358

    申请日：2012-07-24

    Applicant: INTEL CORP

    Inventor： KOKER ATLUG ,  SANKARAN RAJESH ,  LANTZ PHILIP ,  MALLICK ASIT ,  CROSSLAND JAMES ,  NAVALE ADITVA ,  NEIGER GILBERT ,  ANDERSON ANDREW

    IPC: G06F12/10 ,  G06F15/80

    Abstract: Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

Patent Agency Ranking