公开(公告)号：JP2013080490A

公开(公告)日：2013-05-02

申请号：JP2012261129

申请日：2012-11-29

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： HUGHES CHRISTOPHER ,  CHEN YEAN-KUANG ,  BOMB MAYANK ,  BRANDT JASON W ,  BUXTON MARK J ,  CHARNEY MARK J ,  CHENNUPATY SRINIVAS ,  CORBAL JESUS ,  DIXON MARTIN G ,  GIRKAR MILIND B ,  HALL JONATHAN C ,  IDO HIDEKI SAITO ,  LACHNER PETER ,  NEIGER GILBERT ,  NEWBURN CHRIS J ,  PARTHASARATHY RAJESH S ,  TOLL BRET L ,  VALENTINE ROBERT ,  WIEDEMEIER JEFFREY G

IPC: G06F9/30 ,  G06F9/48 ,  G06F11/28 ,  G06F12/10 ,  G06F17/16

CPC classification number: G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3865

Abstract: PROBLEM TO BE SOLVED: To provide a processor which reduces overhead in gathering and scattering multiple data elements.SOLUTION: Efficient data transfer operations can be achieved by: decoding by a processor device 140, 160, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an operation execution unit in the processor; detecting occurrence of an exception during execution of the single instruction; and, in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

Abstract translation: 要解决的问题：提供一种减少收集和散射多个数据元素的开销的处理器。 解决方案：可以通过以下方式来实现有效的数据传送操作：由处理器设备140,160解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出由处理器中的操作执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2011134318A

公开(公告)日：2011-07-07

申请号：JP2010273399

申请日：2010-12-08

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： HUGHES CHRISTOPHER ,  CHEN YEAN-KUANG ,  BOMB MAYANK ,  BRANDT JASON W ,  BUXTON MARK J ,  CHARNEY MARK J ,  CHENNUPATY SRINIVAS ,  CORBAL JESUS ,  DIXON MARTIN G ,  GIRKAR MILIND B ,  HALL JONATHAN C ,  IDO HIDEKI SAITO ,  LACHNER PETER ,  NEIGER GILBERT ,  NEWBURN CHRIS J ,  PARTHASARATHY RAJESH S ,  TOLL BRET L ,  VALENTINE ROBERT ,  WIEDEMEIER JEFFREY G

IPC: G06F9/30 ,  G06F9/48 ,  G06F12/08 ,  G06F15/80

CPC classification number: G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3865

Abstract: PROBLEM TO BE SOLVED: To achieve to gather and scatter multiple data elements.
SOLUTION: Efficient data transfer processing can be achieved by: a step of decoding by a processor device, a single instruction specifying transfer processing for a plurality of data elements between a first storage area and a second storage area; a step of issuing the single instruction for execution by an execution unit in the processor; a step of detecting the occurrence of an exception during execution of the single instruction; and in response to the exception, a step of delivering pending traps or interrupts to an exception handler before delivering the exception.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：实现收集和分散多个数据元素。 解决方案：可以通过以下步骤来实现有效的数据传送处理：由处理器设备解码的步骤，指定在第一存储区域和第二存储区域之间的多个数据元素的传送处理的单个指令; 发出处理器中由执行单元执行的单个指令的步骤; 在单个指令的执行期间检测异常的发生的步骤; 并且响应于异常，在传递异常之前，将异常陷阱或中断传递到异常处理程序的步骤。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2017030625A3

公开(公告)日：2017-04-13

申请号：PCT/US2016035195

申请日：2016-06-01

Applicant: INTEL CORP

Inventor： BRANDT JASON W ,  SHANBHOGUE VEDVYAS

IPC: H04L9/08

CPC classification number: H04L9/0894

Abstract: Embodiments of an invention for loading and virtualizing cryptographic keys are disclosed. In one embodiment, a processor includes a local key storage location, a backup key storage location, and execution hardware. Neither the local key storage location nor the backup key storage location is readable by software. The execution hardware is to perform a first operation and a second operation. The first operation includes loading a cryptographic key into the local key storage location. The second operation includes copying the cryptographic key from the local key storage location to the backup key storage location.

Abstract translation: 公开了用于加载和虚拟化密码密钥的发明的实施例。 在一个实施例中，处理器包括本地密钥存储位置，备份密钥存储位置和执行硬件。 本地密钥存储位置和备份密钥存储位置都不被软件读取。 执行硬件是执行第一操作和第二操作。 第一操作包括将加密密钥加载到本地密钥存储位置。 第二操作包括将加密密钥从本地密钥存储位置复制到备份密钥存储位置。

公开(公告)号：WO2017030625A9

公开(公告)日：2017-03-16

申请号：PCT/US2016035195

申请日：2016-06-01

Applicant: INTEL CORP

Inventor： BRANDT JASON W ,  SHANBHOGUE VEDVYAS

IPC: H04L9/08

CPC classification number: H04L9/0894

Abstract: Embodiments of an invention for loading and virtualizing cryptographic keys are disclosed. In one embodiment, a processor includes a local key storage location, a backup key storage location, and execution hardware. Neither the local key storage location nor the backup key storage location is readable by software. The execution hardware is to perform a first operation and a second operation. The first operation includes loading a cryptographic key into the local key storage location. The second operation includes copying the cryptographic key from the local key storage location to the backup key storage location.

Abstract translation: 公开了用于加载和虚拟化密钥的发明的实施例。 在一个实施例中，处理器包括本地密钥存储位置，备份密钥存储位置和执行硬件。 软件不能读取本地密钥存储位置和备份密钥存储位置。 执行硬件将执行第一操作和第二操作。 第一个操作包括将加密密钥加载到本地密钥存储位置。 第二操作包括将密码密钥从本地密钥存储位置复制到备份密钥存储位置。

公开(公告)号：GB2514236A

公开(公告)日：2014-11-19

申请号：GB201404549

申请日：2014-03-14

Applicant: INTEL CORP

Inventor： WEISSMANN ELIERZER ,  RAPPOPORT RINAT ,  MISHAELI MICHAEL ,  SHAFI HISHAM ,  LENZ ORON ,  BRANDT JASON W ,  FISCHER STEPHEN A ,  TOLL BRET L ,  SODHI INDER M ,  NAVEH ALON ,  SPRINIVASA GANAPATI ,  CHOUBAL ASHISH ,  HAHN SCOTT D ,  KOUFATY DAVID A ,  FENGER RUSSEL J ,  KHANNA GAURAV ,  GORBATOV EUGENE ,  NAIK MISHALI ,  HERDRICH ANDREW J ,  PRABHAKARAN ABIRAMI ,  JAHAGIRDAR SANJEEV ,  BRETT PAUL ,  NARVAEZ PAOLO ,  HENROID ANDREW D ,  SUBBAREDDY DHEERAJ R

IPC: G06F9/50 ,  G06F1/32

Abstract: A heterogeneous processor comprises a first physical core having a first instruction set and a first power consumption level, to execute a thread at a first performance level, and a second physical core having a second instruction set and a second power consumption level, to execute a thread at a second performance level. A virtual-to-physical mapping circuit is coupled to the first and second physical cores. The first physical core is mapped to a system firmware interface via a virtual core, and the second physical core is hidden from the system firmware interface. A single physical core may act as a bootstrap processor. The first physical core may act as the bootstrap processor and this may initialize the second physical core. In another embodiment there is a set of one or more small physical cores and at least one large processor core. Two or more small physical cores are exposed to a system firmware interface and the large physical core is hidden from the system firmware interface.

公开(公告)号：DE102010053088A1

公开(公告)日：2011-06-30

申请号：DE102010053088

申请日：2010-12-01

Applicant: INTEL CORP

Inventor： HUGHES CHRISTOPHER ,  CHEN YEN-KUANG Y K ,  BOMB MAYANK ,  BRANDT JASON W ,  BUXTON MARK J ,  CHARNEY MARK J ,  CHENNUPATY SRINIVAS ,  CORBAL JESUS ,  DIXON MARTIN G ,  GIRKAR MILIND B ,  HALL JONATHAN C ,  IDO HIDEKI SAITO ,  LACHNER PETER ,  NEIGER GILBERT ,  NEWBURN CHRIS J ,  PARTHASARATHY RAJESH S ,  TOLL BRET L ,  VALENTINE ROBERT ,  WIEDEMEIER JEFFREY G

IPC: G06F9/315 ,  G06F9/30

Abstract: Gemäß einem ersten Aspekt können effiziente Datentransferoperationen erreicht werden durch: Decodieren, durch ein Prozessorgerät, eines einzelnen Befehls, der eine Transferoperation für eine Vielzahl von Datenelementen zwischen einem ersten Speicherort und einem zweiten Speicherort spezifiziert; Ausgeben eines einzelnen Befehls zum Ausführen durch eine Ausführungseinheit in dem Prozessor; Erkennen eines Vorkommens einer Ausnahme während des Ausführens des einzelnen Befehls; und, als Antwort auf die Ausnahme, Liefern von ausstehenden Traps oder Unterbrechungen an einen Ausnahmenverarbeiter, bevor die Ausnahme geliefert wird.

公开(公告)号：EP3210149A4

公开(公告)日：2018-05-23

申请号：EP15853035

申请日：2015-08-27

Applicant: INTEL CORP

Inventor： SHANBHOGUE VEDVYAS ,  SAHITA RAVI L ,  BULYGIN YURIY ,  LI XIAONING ,  BRANDT JASON W

IPC: G06F21/52 ,  G06F21/56

CPC classification number: G06F21/52

Abstract: In one embodiment, a processor comprises: a first register to store a first bound value for a stack to be stored in a memory; a second register to store a second bound value for the stack; a checker logic to determine, prior to an exit point at a conclusion of a function to be executed on the processor, whether a value of a stack pointer is within a range between the first bound value and the second bound value; and a logic to prevent a return to a caller of the function if the stack pointer value is not within the range. Other embodiments are described and claimed.

公开(公告)号：EP2836906A4

公开(公告)日：2016-01-27

申请号：EP12872443

申请日：2012-03-30

Applicant: INTEL CORP

Inventor： NGUYEN HUY V ,  BRANDT JASON W ,  TYLER JONATHAN J

IPC: G06F9/06 ,  G06F11/34 ,  G06F11/36 ,  G06F13/14 ,  G06F13/38

CPC classification number: G06F9/30003 ,  G06F11/3471 ,  G06F11/3476 ,  G06F11/3636 ,  G06F11/3648 ,  G06F11/3656 ,  G06F2201/805

Abstract: An apparatus and method are described for real time instruction tracing. For example, a method according to one embodiment comprises: recording user specified address ranges for which tracing is required; monitoring a next linear instruction pointer (NLIP) values and/or branch linear instruction pointer (BLIP) values to determine if address range has been entered; when the range is entered, compressing the NLIP and/or BLIP values and constructing fixed length packets containing the tracing data; and transferring the fixed length packets to a memory execution cluster.

公开(公告)号：EP3005127A4

公开(公告)日：2017-01-25

申请号：EP14808307

申请日：2014-05-30

Applicant: INTEL CORP

Inventor： PATEL BAIJU V ,  LI XIAONING ,  ANVIN H P ,  MALLICK ASIT K ,  NEIGER GILBERT ,  CROSSLAND JAMES B ,  OPFERMAN TOBY ,  KHARE ATUL A ,  BRANDT JASON W ,  COKE JAMES S ,  VAJDA BRIAN L

IPC: G06F12/14 ,  G06F9/30 ,  G06F9/45 ,  G06F12/02 ,  G06F21/52

CPC classification number: G06F12/145 ,  G06F8/434 ,  G06F9/30105 ,  G06F9/30134 ,  G06F21/52

Abstract: An example processing system may comprise: a lower stack bound register configured to store a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register configured to store a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic configured to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address.

Abstract translation: 示例性处理系统可以包括：下层堆栈绑定寄存器，被配置为存储第一存储器地址，第一存储器地址标识经由堆栈段可寻址的存储器的下限; 上堆栈绑定寄存器，被配置为存储第二存储器地址，所述第二存储器地址通过所述堆栈段识别所述存储器可寻址的上限; 以及堆栈边界检查逻辑，其被配置为通过将经由所述堆栈段访问的存储器地址与所述第一存储器地址和所述第二存储器地址中的至少一个进行比较来检测未授权堆栈的转动。

公开(公告)号：EP2798771A4

公开(公告)日：2015-10-07

申请号：EP11878687

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： COX GEORGE W ,  JOHNSTON DAVID ,  DIXON MARTIN G ,  FISCHER STEPHEN A ,  BRANDT JASON W

IPC: H04L9/22 ,  G06F7/58 ,  G06F9/30 ,  H04L9/06 ,  H04L9/08

CPC classification number: H04L9/0869 ,  G06F7/588 ,  G06F9/30007 ,  H04L9/0662 ,  H04L2209/24