公开(公告)号：GB2493880A

公开(公告)日：2013-02-20

申请号：GB201221421

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A first processor 101, such as a central processing unit (CPU), is in a cache coherency domain with a first set of coherency rules 109. Another processor 105, such as a graphics processing unit (GPU), is in a different coherency domain 111 with a second set of coherency rules. The first processor has a level 1 processor cache 103 (L1 cache) and a lower level processor cache 107. The second processor has a level 1 graphics cache 104 (L1 cache) and a lower level cache 108. The first processor uses the first set of coherency rules with the lower level graphics cache. The second processor uses the second set of coherency rules with the lower level graphics cache. The lower level graphics cache may be a mid-level or last level cache. The first processor may snoop the lower level graphics cache.

公开(公告)号：GB2495032B

公开(公告)日：2013-05-08

申请号：GB201222945

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：GB2493880B

公开(公告)日：2013-03-27

申请号：GB201221421

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：GB2490821B

公开(公告)日：2013-01-30

申请号：GB201214187

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：GB2506788A

公开(公告)日：2014-04-09

申请号：GB201400358

申请日：2012-07-24

Applicant: INTEL CORP

Inventor： KOKER ATLUG ,  SANKARAN RAJESH ,  LANTZ PHILIP ,  MALLICK ASIT ,  CROSSLAND JAMES ,  NAVALE ADITVA ,  NEIGER GILBERT ,  ANDERSON ANDREW

IPC: G06F12/10 ,  G06F15/80

Abstract: Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

公开(公告)号：GB2495032A

公开(公告)日：2013-03-27

申请号：GB201222945

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A processor 101, such as a central processing unit (CPU), is in a cache coherency domain with a first set of coherency rules 109. A graphics device 105, such as a graphics processing unit (GPU), is in a different coherency domain 111 with a second set of coherency rules. The processor has a level 1 processor cache 103 (L1 cache) and a lower level processor cache 107. The graphics device has a level 1 graphics cache 104 (L1 cache) and a lower level graphics cache 108. The central processing unit uses the first set of coherency rules with the lower level graphics cache. The graphics device uses the second set of coherency rules with the lower level graphics cache. The lower level graphics cache may be a mid-level or last level cache. The processor may snoop the lower level graphics cache.

公开(公告)号：GB2490821A

公开(公告)日：2012-11-14

申请号：GB201214187

申请日：2009-03-27

Applicant: INTEL CORP

Inventor： OFFEN ZEEV ,  BERKOVITS ARIEL ,  PIAZZA THOMAS A ,  FARRELL ROBERT L ,  KOKER ATLUG ,  KAHN OPER

IPC: G06F12/08

Abstract: A processor 101, such as a central processing unit (CPU), is in a cache coherency domain with a first set of coherency rules 109. A graphics device 105, such as a graphics processing unit (GPU), is in a different coherency domain 111 with a second set of coherency rules. The processor has a level 1 processor cache 103 (L1 cache) and a lower level processor cache 107. The graphics device has a level 1 graphics cache 104 (L1 cache) and a lower level graphics cache 108. The central processing unit uses the first set of coherency rules with the lower level graphics cache. The graphics device uses the second set of coherency rules with the lower level graphics cache. The lower level graphics cache may be a mid-level or last level cache. The processor may snoop the lower level graphics cache.