公开(公告)号：WO2013101078A8

公开(公告)日：2013-09-06

申请号：PCT/US2011067865

申请日：2011-12-29

Applicant: INTEL CORP ,  GIBERT CODINA ENRIC ,  LATORRE FERNANDO ,  CODINA JOSEP M ,  GOMEZ REQUENA CRISPIN ,  GONZALEZ ANTONIO ,  HYUSEINOVA MEYREM ,  KOTSELIDIS CHRISTOS E ,  LOPEZ PEDRO ,  LUPON MARC ,  MADRILES CARLOS ,  MAGKLIS GRIGORIOS ,  MARCUELLO PEDRO ,  MARTINEZ VICENTE ALEJANDRO ,  MARTINEZ RAUL ,  ORTEGA DANIEL ,  PAVLOU DEMOS ,  STAVROU KYRIAKOS A ,  TOURNAVITIS GEORGIOS ,  XEKALAKIS POLYCHRONIS

Inventor： GIBERT CODINA ENRIC ,  LATORRE FERNANDO ,  CODINA JOSEP M ,  GOMEZ REQUENA CRISPIN ,  GONZALEZ ANTONIO ,  HYUSEINOVA MEYREM ,  KOTSELIDIS CHRISTOS E ,  LOPEZ PEDRO ,  LUPON MARC ,  MADRILES CARLOS ,  MAGKLIS GRIGORIOS ,  MARCUELLO PEDRO ,  MARTINEZ VICENTE ALEJANDRO ,  MARTINEZ RAUL ,  ORTEGA DANIEL ,  PAVLOU DEMOS ,  STAVROU KYRIAKOS A ,  TOURNAVITIS GEORGIOS ,  XEKALAKIS POLYCHRONIS

IPC: G06F9/06 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F2212/507

Abstract: Techniques are described for providing an enhanced cache coherency protocol for a multi-core processor that includes a Speculative Request For Ownership Without Data (SRFOWD) for a portion of cache memory. With a SRFOWD, only an acknowledgement message may be provided as an answer to a requesting core. The contents of the affected cache line are not required to be a part of the answer. The enhanced cache coherency protocol may assure that a valid copy of the current cache line exists in case of misspeculation by the requesting core. Thus, an owner of the current copy of the cache line may maintain a copy of the old contents of the cache line. The old contents of the cache line may be discarded if speculation by the requesting core turns out to be correct. Otherwise, in case of misspeculation by the requesting core, the old contents of the cache line may be set back to a valid state.

Abstract translation: 描述了用于为多核处理器提供增强的高速缓存一致性协议的技术，所述多核处理器包括用于高速缓冲存储器的一部分的无数据的所有权投标请求（SRFOWD）。 使用SRFOWD，可以仅提供确认消息作为请求内核的答案。 受影响的缓存行的内容不需要作为答案的一部分。 增强的高速缓存一致性协议可以确保在请求核心的错误配置的情况下存在当前高速缓存行的有效副本。 因此，高速缓存行的当前副本的所有者可以维护高速缓存行的旧内容的副本。 如果请求的核心的猜测证明是正确的，则可以丢弃该高速缓存行的旧内容。 否则，在请求核心发生错误的情况下，可以将高速缓存行的旧内容设置回有效状态。

公开(公告)号：WO2006122990A3

公开(公告)日：2008-07-03

申请号：PCT/ES2005000279

申请日：2005-05-19

Applicant: INTEL CORP ,  MADRILES CARLOS ,  RUNDBERG PETER ,  SANCHEZ JESUS ,  GARCIA CARLOS ,  MARCUELLO PEDRO ,  GONZALEZ ANTONIO

Inventor： MADRILES CARLOS ,  RUNDBERG PETER ,  SANCHEZ JESUS ,  GARCIA CARLOS ,  MARCUELLO PEDRO ,  GONZALEZ ANTONIO

IPC: G06F9/38

CPC classification number: G06F9/3824 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851

Abstract: The invention relates to a multiversion storage configuration which can store multiple values per speculative set of instructions for one storage position in order to enable the real-time precalculation and execution of the body of the set of instructions from a speculative instruction set. The invention also relates to the validation of the input values which can be calculated and used in the execution of the speculative instruction set. The invention further relates to a method of performing said validation step.

Abstract translation: 本发明涉及一种多维度存储配置，其可以为每个用于一个存储位置的每个推测的指令集存储多个值，以便能够从推测性指令集中实时预先计算和执行该组指令的正文。 本发明还涉及可以在推测指令集的执行中计算和使用的输入值的验证。 本发明还涉及一种执行所述验证步骤的方法。

公开(公告)号：SG10201807923YA

公开(公告)日：2018-10-30

申请号：SG10201807923Y

申请日：2015-04-30

Applicant: INTEL CORP

Inventor： FERNANDEZ JUAN ,  CARRETERO CASADO JAVIER ,  MARCUELLO PEDRO ,  AKENINE-MÖLLER TOMAS G

Abstract: EXPLOITING FRAME TO FRAME COHERENCY IN A SORT-MIDDLE ARCHITECTURE Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame. Fig. 2

公开(公告)号：EP2798470A4

公开(公告)日：2015-07-15

申请号：EP11878987

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： STAVROU KYRIAKOS A ,  GIBERT CODINA ENRIC ,  CODINA JOSEP M ,  GOMEZ REQUENA CRISPIN ,  GONZALEZ ANTONIO ,  HYUSEINOVA MIREM ,  KOTSELIDIS CHRISTOS E ,  LATORRE FERNANDO ,  LOPEZ PEDRO ,  LUPON MARC ,  MADRILES CARLOS ,  MAGKLIS GRIGORIOS ,  MARCUELLO PEDRO ,  MARTINEZ VICENTE ALEJANDRO ,  MARTINEZ RAUL ,  ORTEGA DANIEL ,  PAVLOU DEMOS ,  TOURNAVITIS GEORGIOS ,  XEKALAKIS POLYCHRONIS

IPC: G06F9/06 ,  G06F9/30

CPC classification number: G06F9/3804 ,  G06F9/30047 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3848 ,  G06F12/0862 ,  G06F2212/452

Abstract: Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

Abstract translation: 公开了一种用于从指令高速缓存管理指令高速缓存预取的装置和方法。 处理器可以包括：预取引擎; 预测分支结果的分支预测引擎; 和动态优化器。 动态优化器可用于控制：识别公共指令高速缓存未命中，并将预取引擎的预取指令插入指令高速缓存。

公开(公告)号：EP3143594A4

公开(公告)日：2017-12-27

申请号：EP15792470

申请日：2015-04-30

Applicant: INTEL CORP

Inventor： FERNANDEZ JUAN ,  CARRETERO CASADO JAVIER ,  MARCUELLO PEDRO ,  AKENINE-MÖLLER TOMAS G

IPC: G06T15/00 ,  G06T11/40

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T17/10 ,  G06T2200/28 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/122

Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.

公开(公告)号：EP2798520A4

公开(公告)日：2016-12-07

申请号：EP11878906

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： MAGKLIS GRIGORIOS ,  CODINA JOSEP M ,  ZILLES CRAIG B ,  NEILLY MICHAEL ,  SAMUDRALA SRIDHAR ,  MARTINEZ VICENTE ALEJANDRO ,  XEKALAKIS POLYCHRONIS ,  SANCHEZ F JESUS ,  LUPON MARC ,  TOURNAVITIS GEORGIOS ,  GIBERT CODINA ENRIC ,  GOMEZ REQUENA CRISPIN ,  GONZALEZ ANTONIO ,  HYUSEINOVA MIREM ,  KOTSELIDIS CHRISTOS E ,  LATORRE FERNANDO ,  LOPEZ PEDRO ,  MADRILES CARLOS ,  MARCUELLO PEDRO ,  MARTINEZ RAUL ,  ORTEGA DANIEL ,  PAVLOU DEMOS ,  STAVROU KYRIAKOS A

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/30032 ,  G06F9/30087 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3842

公开(公告)号：RU2677584C1

公开(公告)日：2019-01-17

申请号：RU2017134050

申请日：2015-04-30

Applicant: INTEL CORP

Inventor： FERNANDEZ JUAN ,  CARRETERO CASADO JAVIER ,  MARCUELLO PEDRO ,  AKENINE-MOLLER TOMAS G

IPC: G06T11/40

Abstract: Изобретениеотноситсяк устройствам, способуи системедляобработкикадровизображения. Техническийрезультатзаключаетсяв повышенииэффективностиобработкикадровизображения. Устройствосодержитграфическийпроцессордлягенерированияидентификационногокода, соответствующегоодномуилиболееизоднородныхпрофилей, данныхо вершинах, координаттекстурыилиграфическогосостояниядляплиткив текущемкадре, определения, имеетсяливызовотрисовки, полностьюпокрывающийплитку, сохраненияидентификационногокодатолькодлявызоваотрисовки, полностьюпокрывающемуплитку, длясоответствующейплиткиизпредыдущегокадрапередвизуализациейплиткив текущемкадре, определения, совпадаетликоддлятекущейплиткив текущемкадрес кодомдлясоответствующейплиткив предыдущемкадре, повторногоиспользования, есликоддляплиткив предыдущемкадреи коддляплиткив текущемкадресовпадают, изображенияизпредыдущегокадрав качествепикселейтекущейплитки, стемчтобыизбежатьвизуализацииплиткив текущемкадре, ибуферкадров, соединенныйс процессором. 4 н. и 28 з.п. ф-лы, 4 ил.

公开(公告)号：SG11201608884PA

公开(公告)日：2016-11-29

申请号：SG11201608884P

申请日：2015-04-30

Applicant: INTEL CORP

Inventor： FERNANDEZ JUAN ,  CARRETERO CASADO JAVIER ,  MARCUELLO PEDRO ,  AKENINE-MÖLLER TOMAS G

IPC: G06T11/40

Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.

公开(公告)号：DE112006003917T5

公开(公告)日：2009-06-04

申请号：DE112006003917

申请日：2006-05-30

Applicant: INTEL CORP

Inventor： GIMENO CARLOS MADRILES ,  QUINONES CARLOS GARCIA ,  MARCUELLO PEDRO ,  SANCHEZ JESES ,  LATORRE FERNANDO ,  GONZALEZ ANTONIO

IPC: G06F12/08 ,  G06F12/0831

Abstract: In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.