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公开(公告)号：JP2012009061A
公开(公告)日：2012-01-12
申请号：JP2011188311
申请日：2011-08-31
Applicant: Intel Corp , インテル・コーポレーション
Inventor： MAGKLIS GRIGORIOS , JOSE GONZALEZ , ANTONIO GONZALEZ
IPC: G06F1/32
CPC classification number: G06F1/06 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F9/3869 , Y02B60/1217 , Y02B60/1285 , Y02D10/126 , Y02D10/172
Abstract: PROBLEM TO BE SOLVED: To provide a technology for dividing a microprocessor into a plurality of clock domains, and for controlling their power consumption.SOLUTION: Disclosed is a device and method for scaling a frequency and operating voltage of at least one clock domain of a microprocessor. As for the clock signal frequency and operating voltage of each clock domain of the processor, a pair of the clock signal frequency and operating voltage minimizing a rate of energy delay square products with respect to first and second time intervals is selected.
Abstract translation: 要解决的问题：提供一种将微处理器分成多个时钟域并用于控制其功耗的技术。 解决方案：公开了一种用于缩放微处理器的至少一个时钟域的频率和工作电压的装置和方法。 对于处理器的每个时钟域的时钟信号频率和工作电压，选择一对时钟信号频率和工作电压，使相对于第一和第二时间间隔的能量延迟平方乘积的速率最小化。 版权所有（C）2012，JPO＆INPIT
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公开(公告)号：DE112005002416T5
公开(公告)日：2007-10-18
申请号：DE112005002416
申请日：2005-11-14
Applicant: INTEL CORP
Inventor： MAGKLIS GRIGORIOS , GONZALEZ JOSE , GONZALEZ ANTONIO
IPC: G06F9/38
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公开(公告)号：WO2013101078A8
公开(公告)日：2013-09-06
申请号：PCT/US2011067865
申请日：2011-12-29
Applicant: INTEL CORP , GIBERT CODINA ENRIC , LATORRE FERNANDO , CODINA JOSEP M , GOMEZ REQUENA CRISPIN , GONZALEZ ANTONIO , HYUSEINOVA MEYREM , KOTSELIDIS CHRISTOS E , LOPEZ PEDRO , LUPON MARC , MADRILES CARLOS , MAGKLIS GRIGORIOS , MARCUELLO PEDRO , MARTINEZ VICENTE ALEJANDRO , MARTINEZ RAUL , ORTEGA DANIEL , PAVLOU DEMOS , STAVROU KYRIAKOS A , TOURNAVITIS GEORGIOS , XEKALAKIS POLYCHRONIS
Inventor： GIBERT CODINA ENRIC , LATORRE FERNANDO , CODINA JOSEP M , GOMEZ REQUENA CRISPIN , GONZALEZ ANTONIO , HYUSEINOVA MEYREM , KOTSELIDIS CHRISTOS E , LOPEZ PEDRO , LUPON MARC , MADRILES CARLOS , MAGKLIS GRIGORIOS , MARCUELLO PEDRO , MARTINEZ VICENTE ALEJANDRO , MARTINEZ RAUL , ORTEGA DANIEL , PAVLOU DEMOS , STAVROU KYRIAKOS A , TOURNAVITIS GEORGIOS , XEKALAKIS POLYCHRONIS
CPC classification number: G06F12/0815 , G06F2212/507
Abstract: Techniques are described for providing an enhanced cache coherency protocol for a multi-core processor that includes a Speculative Request For Ownership Without Data (SRFOWD) for a portion of cache memory. With a SRFOWD, only an acknowledgement message may be provided as an answer to a requesting core. The contents of the affected cache line are not required to be a part of the answer. The enhanced cache coherency protocol may assure that a valid copy of the current cache line exists in case of misspeculation by the requesting core. Thus, an owner of the current copy of the cache line may maintain a copy of the old contents of the cache line. The old contents of the cache line may be discarded if speculation by the requesting core turns out to be correct. Otherwise, in case of misspeculation by the requesting core, the old contents of the cache line may be set back to a valid state.
Abstract translation: 描述了用于为多核处理器提供增强的高速缓存一致性协议的技术，所述多核处理器包括用于高速缓冲存储器的一部分的无数据的所有权投标请求（SRFOWD）。 使用SRFOWD，可以仅提供确认消息作为请求内核的答案。 受影响的缓存行的内容不需要作为答案的一部分。 增强的高速缓存一致性协议可以确保在请求核心的错误配置的情况下存在当前高速缓存行的有效副本。 因此，高速缓存行的当前副本的所有者可以维护高速缓存行的旧内容的副本。 如果请求的核心的猜测证明是正确的，则可以丢弃该高速缓存行的旧内容。 否则，在请求核心发生错误的情况下，可以将高速缓存行的旧内容设置回有效状态。
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公开(公告)号：WO2006057865A3
公开(公告)日：2006-12-14
申请号：PCT/US2005041392
申请日：2005-11-14
Applicant: INTEL CORP , MAGKLIS GRIGORIOS , GONZALEZ JOSE , GONZALEZ ANTONIO
Inventor： MAGKLIS GRIGORIOS , GONZALEZ JOSE , GONZALEZ ANTONIO
CPC classification number: G06F1/06 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F9/3869 , Y02B60/1217 , Y02B60/1285 , Y02D10/126 , Y02D10/172
Abstract: A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.
Abstract translation: 一种用于缩放微处理器的至少一个时钟域的频率和工作电压的方法和设备。 更具体地说，本发明的实施例涉及将微处理器分成时钟域并独立于每个时钟域来控制每个时钟域的频率和工作电压的技术。
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Patent Agency Ranking
公开(公告)号：GB2457752B
公开(公告)日：2010-05-05
申请号：GB0900831
申请日：2006-06-30
Applicant: INTEL CORP
Inventor： MONFERRER PEDRO CHAPARRO , MAGKLIS GRIGORIOS , GONZALEZ JOSE , GONZALEZ ANTONIO
Abstract: Methods and apparatus to provide leakage power estimation are described. In one embodiment, one or more sensed temperature values (108) and one or more voltage values (110) are utilized to determine the leakage power of an integrated circuit (IC) component. Other embodiments are also described.
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公开(公告)号：DE112005002416B4
公开(公告)日：2009-04-30
申请号：DE112005002416
申请日：2005-11-14
Applicant: INTEL CORP
Inventor： MAGKLIS GRIGORIOS , GONZALEZ JOSE , GONZALEZ ANTONIO
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公开(公告)号：GB2457752A
公开(公告)日：2009-08-26
申请号：GB0900831
申请日：2006-06-30
Applicant: INTEL CORP
Inventor： MONFERRER PEDRO CHAPARRO , MAGKLIS GRIGORIOS , GONZALEZ JOSE , GONZALEZ ANTONIO
Abstract: The invention concerns methods and devices for providing leakage power estimation. In one embodiment, one or more detected temperature values (108) and one or more voltage values (110) are used to determine the leakage power of an integrated circuit (IC) component. The invention further relates to other embodiments.
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公开(公告)号：EP2798470A4
公开(公告)日：2015-07-15
申请号：EP11878987
申请日：2011-12-29
Applicant: INTEL CORP
Inventor： STAVROU KYRIAKOS A , GIBERT CODINA ENRIC , CODINA JOSEP M , GOMEZ REQUENA CRISPIN , GONZALEZ ANTONIO , HYUSEINOVA MIREM , KOTSELIDIS CHRISTOS E , LATORRE FERNANDO , LOPEZ PEDRO , LUPON MARC , MADRILES CARLOS , MAGKLIS GRIGORIOS , MARCUELLO PEDRO , MARTINEZ VICENTE ALEJANDRO , MARTINEZ RAUL , ORTEGA DANIEL , PAVLOU DEMOS , TOURNAVITIS GEORGIOS , XEKALAKIS POLYCHRONIS
CPC classification number: G06F9/3804 , G06F9/30047 , G06F9/3017 , G06F9/3802 , G06F9/3806 , G06F9/3848 , G06F12/0862 , G06F2212/452
Abstract: Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
Abstract translation: 公开了一种用于从指令高速缓存管理指令高速缓存预取的装置和方法。 处理器可以包括：预取引擎; 预测分支结果的分支预测引擎; 和动态优化器。 动态优化器可用于控制：识别公共指令高速缓存未命中，并将预取引擎的预取指令插入指令高速缓存。
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公开(公告)号：EP2798520A4
公开(公告)日：2016-12-07
申请号：EP11878906
申请日：2011-12-29
Applicant: INTEL CORP
Inventor： MAGKLIS GRIGORIOS , CODINA JOSEP M , ZILLES CRAIG B , NEILLY MICHAEL , SAMUDRALA SRIDHAR , MARTINEZ VICENTE ALEJANDRO , XEKALAKIS POLYCHRONIS , SANCHEZ F JESUS , LUPON MARC , TOURNAVITIS GEORGIOS , GIBERT CODINA ENRIC , GOMEZ REQUENA CRISPIN , GONZALEZ ANTONIO , HYUSEINOVA MIREM , KOTSELIDIS CHRISTOS E , LATORRE FERNANDO , LOPEZ PEDRO , MADRILES CARLOS , MARCUELLO PEDRO , MARTINEZ RAUL , ORTEGA DANIEL , PAVLOU DEMOS , STAVROU KYRIAKOS A
CPC classification number: G06F9/3001 , G06F9/30032 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3842
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