公开(公告)号：WO2011059574A2

公开(公告)日：2011-05-19

申请号：PCT/US2010050013

申请日：2010-09-23

Applicant: INTEL CORP ,  SCHMIDT DAREN J ,  WHITE BRYAN R

Inventor： SCHMIDT DAREN J ,  WHITE BRYAN R

CPC classification number: H04L47/39 ,  G06F12/0831 ,  G06F13/385 ,  G06F13/4068 ,  G06F13/4221 ,  G06F2213/3808 ,  H04L47/30

Abstract: In one embodiment, the present invention provides for a layered communication protocol for a serial link, in which a link layer is to receive and forward a message to a protocol layer coupled to the link layer with a minimal amount of buffering and without maintenance of a single resource buffer for adaptive credit pools where all message classes are able to consume credits. By performing a message decode, the link layer is able to steer non-data messages and data messages to separate structures within the protocol layer. Credit accounting for each message type can be handled independently where the link layer is able to return credits immediately for non-data messages. In turn, the protocol layer includes a shared buffer to store all data messages received from the link layer and return credits to the link layer for these messages when the data is removed from the shared buffer. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明提供了用于串行链路的分层通信协议，其中链路层将以最小量的缓冲接收和转发消息到与链路层耦合的协议层，并且不维护 用于自适应信用库的单个资源缓冲区，其中所有消息类都能够消耗信用。 通过执行消息解码，链路层能够引导非数据消息和数据消息来分离协议层内的结构。 每个消息类型的信用记帐可以独立处理，链路层可以立即为非数据消息返回信用。 反过来，协议层包括共享缓冲器，用于存储从链路层接收到的所有数据消息，并且当数据从共享缓冲器中移除时，向这些消息的链路层返回信用。 描述和要求保护其他实施例。

公开(公告)号：WO2005066827A2

公开(公告)日：2005-07-21

申请号：PCT/US2004043687

申请日：2004-12-23

Applicant: INTEL CORP ,  SCHMIDT DAREN J ,  PUFFER DAVID M ,  KOTAMREDDY SARATH ,  RENAUD LYONEL

Inventor： SCHMIDT DAREN J ,  PUFFER DAVID M ,  KOTAMREDDY SARATH ,  RENAUD LYONEL

IPC: G06F5/10 ,  G06F5/14 ,  G06F15/16

CPC classification number: G06F5/14

Abstract: A number of symbols are received in a first integrated circuit (IC) device, where these symbols have been transmitted by a second IC device and are received over a serial point to point link. These symbols include a non-data sequence that has been inserted into a data sequence by the second device. The symbols are loaded into a buffer. The data sequence and some of the non-data sequence is unloaded from the buffer, according to a changing unload pointer. To prevent overflow of the buffer, and in response to detecting the non-data sequence, the unload pointer is changed by more than one entry so that a non-­data symbol of the non-data sequence as loaded in the buffer is skipped while unloading from the buffer. In another embodiment, to prevent underflow of the buffer, the unload pointer is stalled at an entry of the buffer that contains a non-data symbol while unloading. Other embodiments are also described and claimed.

Abstract translation: 在第一集成电路（IC）装置中接收多个符号，其中这些符号已由第二IC器件传输并通过串行点对点链接接收。 这些符号包括已被第二设备插入到数据序列中的非数据序列。 符号被加载到缓冲区。 根据改变的卸载指针，数据序列和一些非数据序列从缓冲区中卸载。 为了防止缓冲器的溢出，并且响应于检测到非数据序列，卸载指针由多个条目改变，使得在卸载期间跳过加载在缓冲器中的非数据序列的非数据符号 从缓冲区。 在另一个实施例中，为了防止缓冲器的下溢，卸载指针在卸载期间在包含非数据符号的缓冲器的条目处被停止。 还描述和要求保护其他实施例。

公开(公告)号：GB2423171A

公开(公告)日：2006-08-16

申请号：GB0608721

申请日：2004-12-22

Applicant: INTEL CORP

Inventor： RENAUD LYONEL ,  PUFFER DAVID M ,  KOTHAMREDDY SARATH ,  SCHMIDT DAREN J ,  MITBANDER SUNEEL G

IPC: G06F13/38 ,  H04L12/56 ,  H04L25/14

Abstract: Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.

公开(公告)号：PL3392838T3

公开(公告)日：2022-03-28

申请号：PL18161816

申请日：2018-03-14

Applicant: INTEL CORP

Inventor： APPU ABHISHEK R ,  SURTI PRASOONKUMAR ,  MYSORE SRIVALLABA ,  DASGUPTA SUBHAJIT ,  AKIBA HIROSHI ,  HOEKSTRA ERIC J ,  HURD LINDA L ,  SCHLUESSLER TRAVIS T ,  SCHMIDT DAREN J

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/50

公开(公告)号：GB2423171B

公开(公告)日：2007-07-25

申请号：GB0608721

申请日：2004-12-22

Applicant: INTEL CORP

Inventor： RENAUD LYONEL ,  PUFFER DAVID M ,  KOTHAMREDDY SARATH ,  SCHMIDT DAREN J ,  MITBANDER SUNEEL G

IPC: G06F13/38 ,  H04L12/56 ,  H04L25/14

Abstract: Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.

公开(公告)号：ES2907728T3

公开(公告)日：2022-04-26

申请号：ES18161816

申请日：2018-03-14

Applicant: INTEL CORP

Inventor： APPU ABHISHEK R ,  SURTI PRASOONKUMAR ,  MYSORE SRIVALLABA ,  DASGUPTA SUBHAJIT ,  AKIBA HIROSHI ,  HOEKSTRA ERIC J ,  HURD LINDA L ,  SCHLUESSLER TRAVIS T ,  SCHMIDT DAREN J

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/50

Abstract: Un aparato, que comprende: un procesador para recibir un flujo de datos entrantes (610) que incluye datos de canal alfa; y una memoria para almacenar una interfaz de programación de aplicación (API); en donde la API es para: encaminar los datos de canal alfa a una unidad de mezcla de coma fija (612) para realizar una o más operaciones de mezcla usando una representación de coma fija de los datos de canal alfa; y estando caracterizado el aparato por que la API es para encaminar adicionalmente el flujo de datos entrantes (610) a una unidad de mezcla de coma flotante (614) para realizar operaciones que implican una representación de coma flotante de los datos entrantes (610), y por que un multiplexor (616) combina una salida de la unidad de mezcla de coma fija con una salida de la unidad de mezcla de coma flotante (614) para proporcionar datos de salida (618) que incluyen datos de mezcla procesados por la unidad de mezcla de coma fija (612).

公开(公告)号：DE112004002567T5

公开(公告)日：2006-12-14

申请号：DE112004002567

申请日：2004-12-22

Applicant: INTEL CORP

Inventor： RENAUD LYONEL ,  PUFFER DAVID M ,  KOTAMREDDY SARATH ,  SCHMIDT DAREN J ,  MITBANDER SUNEEL G

IPC: G06F13/38 ,  H04L12/56 ,  H04L25/14

Abstract: Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.