公开(公告)号：US20180331053A1

公开(公告)日：2018-11-15

申请号：US15776474

申请日：2015-12-21

Applicant: Intel IP Corporation

Inventor： Christian GEISSLER ,  Sven ALBERS ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Klaus REINGRUBER ,  Thomas WAGNER ,  Marc DITTES

IPC: H01L23/00

Abstract: An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.

公开(公告)号：US20180204831A1

公开(公告)日：2018-07-19

申请号：US15743996

申请日：2015-09-14

Applicant: Intel IP Corporation

Inventor： Georg SEIDEMANN ,  Christian GEISSLER ,  Klaus REINGRUBER

IPC: H01L27/02 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L27/0296 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L27/0255 ,  H01L28/00 ,  H01L2224/02166 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13007 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48157 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/19107 ,  H01L2924/014 ,  H01L2224/45099

Abstract: An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.

公开(公告)号：US20180358317A1

公开(公告)日：2018-12-13

申请号：US15776051

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Sven ALBERS ,  Klaus REINGRUBER ,  Georg SEIDEMANN ,  Christian GEISSLER ,  Richard PATTEN

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/552 ,  H01L23/433 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48

Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US20180226377A1

公开(公告)日：2018-08-09

申请号：US15748115

申请日：2015-08-27

Applicant: INTEL IP CORPORATION

Inventor： Christian GEISSLER ,  Georg SEIDEMANN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/02 ,  H05K1/11

CPC classification number: H01L25/065 ,  H01L21/02362 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0652 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05022 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/0518 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05638 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/24137 ,  H01L2224/27849 ,  H01L2224/291 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2924/01029 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3512 ,  H01L2924/35121 ,  H05K1/111 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/014

Abstract: Embodiments may relate to an embedded package having a diffusion barrier layer may be placed between a copper (Cu) pad and a solder ball inside the embedded package. During the solder reflow process, an intermetallic compound (IMC) layer is created that does not come into contact with the Cu, so that subsequent high temperatures applied to the embedded package may not cause the Cu to be consumed through diffusion. Other embodiments may be described and/or claimed.

公开(公告)号：US20180218962A1

公开(公告)日：2018-08-02

申请号：US15748475

申请日：2015-08-31

Applicant: INTEL IP CORPORATION

Inventor： Christian GEISSLER ,  Georg SEIDEMANN ,  Sonja KOLLER ,  Jan PROSCHWITZ

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3675 ,  H01L21/563 ,  H01L23/13 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/073 ,  H01L25/074 ,  H01L2224/13024 ,  H01L2224/16227 ,  H01L2224/32141 ,  H01L2224/32507 ,  H01L2224/33519 ,  H01L2924/15153

Abstract: Embodiments herein generally relate to the field of package assembly to facilitate thermal conductivity. A package may have a hanging die, and attach to a printed circuit board (PCB). The package may have an active side plane and an inactive side plane opposite the first active side plane. The package may also have a ball grid array (BGA) matrix having a height determined by a distance of a furthest point of the BGA matrix from the active side plane of the package. The package may have a hanging die attached to the active side plane of the package, the hanging die having a z-height greater than the BGA matrix height. When package is attached to the PCB, the hanging die may fit into an area on the PCB that is recessed or has been cut away, and a thermal conductive material may connect the hanging die and the PCB.

公开(公告)号：US20200273832A1

公开(公告)日：2020-08-27

申请号：US16871325

申请日：2020-05-11

Applicant: Intel IP Corporation

Inventor： Sven ALBERS ,  Klaus REINGRUBER ,  Georg SEIDEMANN ,  Christian GEISSLER ,  Richard PATTEN

IPC: H01L23/00 ,  H01L23/433 ,  H01L21/56 ,  H01L23/552 ,  H01L21/48 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US20200176436A1

公开(公告)日：2020-06-04

申请号：US15776378

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Sven ALBERS ,  Klaus REINGRUBER ,  Richard PATTEN ,  Georg SEIDEMANN ,  Christian GEISSLER

IPC: H01L25/00 ,  H01L25/065

Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.

公开(公告)号：US20190206833A1

公开(公告)日：2019-07-04

申请号：US15772730

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Thorsten MEYER ,  Klaus REINGRUBER ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Christian GEISSLER ,  Sven ALBERS

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L25/0652 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/12 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L25/065 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106

Abstract: Embodiments of the invention include an eWLB or ePLB based PoP device and methods of forming such devices. According to an embodiment, such a device may include a die embedded within a mold layer. A substrate may be directly contacting a surface of the mold layer. Additionally, embodiments of the invention may include a through mold via formed through the mold layer that is electrically coupled to a contact formed on a surface of the substrate that is contacting the mold layer. In order to form such a device, embodiments may include dispensing a molding material over a die positioned on a mold carrier. Thereafter, a substrate may be pressed into the molding material. After curing the molding material, a mold layer may be formed that encases the die and is adhered to the substrate.

公开(公告)号：US20180331070A1

公开(公告)日：2018-11-15

申请号：US15774906

申请日：2015-12-26

Applicant: Intel IP Corporation

Inventor： Georg SEIDEMANN ,  Klaus REINGRUBER ,  Christian GEISSLER ,  Sven ALBERS ,  Andreas WOLTER ,  Marc DITTES ,  Richard PATTEN

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

公开(公告)号：US20160329272A1

公开(公告)日：2016-11-10

申请号：US14779967

申请日：2014-12-19

Applicant: Intel IP Corporation

Inventor： Christian GEISSLER ,  Georg SEIDEMANN ,  Klaus REINGRUBER

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/528

CPC classification number: H01L23/49827 ,  H01L23/48 ,  H01L23/49811 ,  H01L23/528 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1421 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19106 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure describes embodiments of a stacked semiconductor device package and associated techniques and configurations. A package may include a packaging substrate having interconnects and a first semiconductor device attached to one side and a second semiconductor device attached to the opposite side. The devices may be attached in a flip chip configuration with pad sides facing each other on opposite sides of the substrate. The devices may be electrically coupled by the interconnects. The devices may be electrically coupled to fan out pads on the substrate. A dielectric layer may be coupled to the second side of the substrate and encapsulate the second device. Vias may route electrical signals from the fan out area through the dielectric layer and into a redistribution layer coupled to the dielectric layer. Other embodiments may be described and/or claimed.

Abstract translation: 本公开描述了堆叠的半导体器件封装和相关联的技术和配置的实施例。 封装可以包括具有互连的封装衬底和附接到一侧的第一半导体器件和附接到相对侧的第二半导体器件。 这些器件可以以倒装芯片配置附接，其中焊盘侧面在衬底的相对侧上彼此面对。 这些器件可以通过互连电耦合。 这些器件可以电耦合到扇出衬底上的焊盘。 电介质层可以耦合到衬底的第二侧并封装第二器件。 通孔可以将来自风扇输出区域的电信号通过电介质层和耦合到电介质层的再分布层布置。 可以描述和/或要求保护其他实施例。