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公开(公告)号:US20220238501A1
公开(公告)日:2022-07-28
申请号:US17583545
申请日:2022-01-25
Applicant: Infineon Technologies AG
Inventor: Stefan Hampl , Marco Haubold , Kerstin Kaemmer , Norbert Thyssen
Abstract: A method for wafer bonding includes: providing a semiconductor wafer having a first main face; fabricating at least one semiconductor device in the semiconductor wafer, wherein the semiconductor device is arranged at the first main face; generating trenches and a cavity in the semiconductor wafer such that the at least one semiconductor device is connected to the rest of the semiconductor wafer by no more than at least one connecting pillar; arranging the semiconductor wafer on a carrier wafer such that the first main face faces the carrier wafer; attaching the at least one semiconductor device to the carrier wafer; and removing the at least one semiconductor device from the semiconductor wafer by breaking the at least one connecting pillar.
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公开(公告)号:US10276494B2
公开(公告)日:2019-04-30
申请号:US15654526
申请日:2017-07-19
Applicant: Infineon Technologies AG
Inventor: Kerstin Kaemmer , Martin Bartels , Henning Feick
IPC: G11C17/16 , H01L23/525 , H01L27/112 , H01L27/102 , G11C17/18
Abstract: Memory cells and corresponding memory arrays are provided. The memory cell comprises a fusable element and a bipolar transistor arranged adjacent to the fusable element.
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公开(公告)号:US20140167184A1
公开(公告)日:2014-06-19
申请号:US13959485
申请日:2013-08-05
Applicant: Infineon Technologies AG
Inventor: Frank Huebinger , Steffen Rothenhaeusser , Kerstin Kaemmer
IPC: H01L21/28 , H01L27/088 , H01L21/283
CPC classification number: H01L21/28008 , H01L21/283 , H01L27/0207 , H01L27/088 , H01L29/6659
Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning a first semi-global region with a first main pattern and patterning a second semi-global region with a second main pattern, wherein the first main pattern is different than the second main pattern. The method further comprises introducing a first dummy pattern in the first semi-global region so that a first sidewall area surface density of the first main pattern and the first dummy pattern in the first semi-global region and a second sidewall area surface density of the second main pattern in the second semi-global region are substantially a same density.
Abstract translation: 公开了一种半导体器件和制造半导体器件的方法。 制造半导体器件的方法包括在衬底上形成材料层,用第一主图案构图第一半全局区域,并用第二主图案构图第二半全局区域,其中第一主图案不同于 第二个主要模式。 该方法还包括在第一半全局区域中引入第一虚拟图案,使得第一主图案和第一半全局区域中的第一虚拟图案的第一侧壁区域表面密度和第一半全局区域的第二侧壁区域表面密度 第二个半全球区域的第二主要模式基本上是相同的密度。
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公开(公告)号:US20210003466A1
公开(公告)日:2021-01-07
申请号:US17024228
申请日:2020-09-17
Applicant: Infineon Technologies AG
Inventor: Rainer Leuschner , Kerstin Kaemmer , Roland Meier , Marten Oldsen , Karolina Zogal
Abstract: A sensor device includes a sensor unit sensitive for a property of a gaseous medium. The sensor unit is formed on a first surface of a sensor substrate. A frame structure on the first surface includes a first loop portion laterally surrounding a first area that includes the sensor unit. A communicating channel accesses the first area through at least one of a lateral port in the first loop portion and a base port in the sensor substrate. A lid structure completely covers the frame structure and the first area.
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5.
公开(公告)号:US20180222744A1
公开(公告)日:2018-08-09
申请号:US15892102
申请日:2018-02-08
Applicant: Infineon Technologies AG
Inventor: Marco Haubold , Henning Feick , Kerstin Kaemmer
IPC: B81B3/00
CPC classification number: B81B3/0021 , B81B3/0086 , B81B2201/0235 , B81B2201/0257 , B81B2201/0264
Abstract: A semiconductor device includes at least one suspension region of a membrane structure, where the suspension region lies laterally in a first region of a surface of a semiconductor substrate; and a membrane region of the membrane structure, where a cavity is arranged vertically between the membrane region and at least one part of the semiconductor substrate, and the first region of the surface of the semiconductor substrate is formed by a surface of a shielding doping region of the semiconductor substrate.
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公开(公告)号:US20230251154A1
公开(公告)日:2023-08-10
申请号:US18304989
申请日:2023-04-21
Applicant: Infineon Technologies AG
Inventor: Rainer Leuschner , Kerstin Kaemmer , Roland Meier , Marten Oldsen , Karolina Zogal
CPC classification number: G01L9/0073 , G01N33/0027 , G01L9/0042
Abstract: A sensor device includes a sensor unit sensitive for a property of a gaseous medium. The sensor unit is formed on a first surface of a sensor substrate. A frame structure on the first surface includes a first loop portion laterally surrounding a first area that includes the sensor unit. A communicating channel accesses the first area through at least one of a lateral port in the first loop portion and a base port in the sensor substrate. A lid structure completely covers the frame structure and the first area.
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公开(公告)号:US10859457B2
公开(公告)日:2020-12-08
申请号:US15808044
申请日:2017-11-09
Applicant: Infineon Technologies AG
Inventor: Rainer Leuschner , Kerstin Kaemmer , Roland Meier , Marten Oldsen , Karolina Zogal
Abstract: A sensor device includes a sensor unit sensitive for a property of a gaseous medium. The sensor unit is formed on a first surface of a sensor substrate. A frame structure on the first surface includes a first loop portion laterally surrounding a first area that includes the sensor unit. A communicating channel accesses the first area through at least one of a lateral port in the first loop portion and a base port in the sensor substrate. A lid structure completely covers the frame structure and the first area.
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公开(公告)号:US10784147B2
公开(公告)日:2020-09-22
申请号:US16029237
申请日:2018-07-06
Applicant: Infineon Technologies AG
Inventor: Ines Uhlig , Kerstin Kaemmer , Norbert Thyssen
IPC: H01L21/762 , H01L21/768 , H01L21/3105 , H01L21/306 , H01L21/3065
Abstract: In accordance with an embodiment, a method for producing a buried cavity structure includes providing a mono-crystalline semiconductor substrate, producing a doped volume region in the mono-crystalline semiconductor substrate, wherein the doped volume region has an increased etching rate for a first etchant by comparison with an adjoining, undoped or more lightly doped material of the monocrystalline semiconductor substrate, forming an access opening to the doped volume region, and removing the doped semiconductor material in the doped volume region using the first etchant through the access opening to obtain the buried cavity structure.
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公开(公告)号:US20180136064A1
公开(公告)日:2018-05-17
申请号:US15808044
申请日:2017-11-09
Applicant: Infineon Technologies AG
Inventor: Rainer Leuschner , Kerstin Kaemmer , Roland Meier , Marten Oldsen , Karolina Zogal
CPC classification number: G01L9/0073 , G01L9/0042 , G01N33/0027
Abstract: A sensor device includes a sensor unit sensitive for a property of a gaseous medium. The sensor unit is formed on a first surface of a sensor substrate. A frame structure on the first surface includes a first loop portion laterally surrounding a first area that includes the sensor unit. A communicating channel accesses the first area through at least one of a lateral port in the first loop portion and a base port in the sensor substrate. A lid structure completely covers the frame structure and the first area.
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10.
公开(公告)号:US09478555B2
公开(公告)日:2016-10-25
申请号:US14927608
申请日:2015-10-30
Applicant: Infineon Technologies AG
Inventor: Kerstin Kaemmer , Thomas Bertrams , Henning Feick , Olaf Storbeck , Matthias Schmeide
IPC: H01L27/11 , H01L27/112 , H01L21/02 , H01L29/51 , H01L23/525 , H01L29/423 , H01L21/265 , H01L21/28
CPC classification number: H01L27/11206 , H01L21/02233 , H01L21/02238 , H01L21/02255 , H01L21/26506 , H01L21/26513 , H01L21/28211 , H01L21/2822 , H01L23/5256 , H01L29/42368 , H01L29/4238 , H01L29/512 , H01L29/513 , H01L2924/0002 , H01L2924/00
Abstract: According to various embodiments, a method for processing a carrier may include: doping a carrier with fluorine such that a first surface region of the carrier is fluorine doped and a second surface region of the carrier is at least one of free from the fluorine doping or less fluorine doped than the first surface region; and oxidizing the carrier to grow a first gate oxide layer from the first surface region of the carrier with a first thickness and simultaneously from the second surface region of the carrier with a second thickness different from the first thickness.
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