中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.021 seconds)

    Electronic module having a three dimensional arrayof carrier-mounted integrated circuit packages
    3.
    发明专利
    Electronic module having a three dimensional arrayof carrier-mounted integrated circuit packages 未知

    公开(公告)号：HK1055015A1

    公开(公告)日：2003-12-19

    申请号：HK03107291

    申请日：2003-10-10

    Applicant: LEGACY ELECTRONICS INC

    Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

    IPC: H01L20060101 ,  H01L25/18 ,  H01L25/10 ,  H01L25/11 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

    Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. Several different variations of the chip module are disclosed.

    Electronic module having a three dimensional array of carrier-mounted integratedcircuit packages
    4.
    发明专利
    Electronic module having a three dimensional array of carrier-mounted integratedcircuit packages 未知

    公开(公告)号：AU4916901A

    公开(公告)日：2001-09-24

    申请号：AU4916901

    申请日：2001-03-13

    Applicant: LEGACY ELECTRONICS INC

    Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

    IPC: H01L25/18 ,  H01L25/10 ,  H01L25/11 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

    Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. Several different variations of the chip module are disclosed.

    MODULO ELECTRONICO QUE TIENE UNA ORDENACION TRIDIMENSIONAL DE PAQUETES DE CIRCUITOS INTEGRADOS MONTADOS EN PORTADORES.
    5.
    发明专利
    MODULO ELECTRONICO QUE TIENE UNA ORDENACION TRIDIMENSIONAL DE PAQUETES DE CIRCUITOS INTEGRADOS MONTADOS EN PORTADORES. 未知

    公开(公告)号：ES2270996T3

    公开(公告)日：2007-04-16

    申请号：ES01922355

    申请日：2001-03-13

    Applicant: LEGACY ELECTRONICS INC

    Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

    IPC: H01L25/10 ,  H01L25/18 ,  H01L23/32 ,  H01L25/11 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

    Abstract: Un portador (100) de paquetes que comprende: un cuerpo (101) dieléctrico que tiene superficies (102U, 102L) planas mayores paralelas superior e inferior; una primera ordenación (103) de tomas de montaje adherida a dicha superficie (102U) plana mayor superior, estando dicha primera ordenación (103) de tomas de montaje dimensionada para recibir los conductores (502) de un primer paquete (501) de circuitos integrados; una segunda ordenación (105) de tomas de montaje adherida a dicha superficie (102L) plana mayor inferior; un conjunto de conductores (108; 701) en el que cada conductor (301, 302, 304; 701) de portador está enlazado conductivamente con una toma (106) de dicha segunda ordenación (105), estando dicho conjunto de conductores (108; 701) de portador espaciado y configurado para el montaje de superficie sobre una placa (503) de circuito impreso; caracterizado porque cada toma (106) de dicha segunda ordenación (105) está acoplada a una toma (104) de dicha primera ordenación (103) por medio de un abertura (107) metalizada interiormente que se extiende entre dicha superficie (102U) plana mayor superior y dicha superficie (102L) mayor inferior; y el portador (100) de paquetes comprende además un pozo (303, 305, 801) de calor incorporado dentro del cuerpo dieléctrico (101) y los conductores (301, 302, 304; 701).

    6.
    发明专利
    未知

    公开(公告)号：AT342583T

    公开(公告)日：2006-11-15

    申请号：AT01922355

    申请日：2001-03-13

    Applicant: LEGACY ELECTRONICS INC

    Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

    IPC: H01L25/18 ,  H01L25/10 ,  H01L25/11 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H01L23/32

    Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. Several different variations of the chip module are disclosed.

    A MODULAR INTEGRATED CIRCUIT CHIP CARRIER
    7.
    发明专利
    A MODULAR INTEGRATED CIRCUIT CHIP CARRIER 未知

    公开(公告)号：MY135660A

    公开(公告)日：2008-06-30

    申请号：MYPI20030627

    申请日：2003-02-24

    Applicant: LEGACY ELECTRONICS INC

    Inventor： KLEDZIK KENNETH J ,  ENGLE JASON

    IPC: H05K1/14 ,  H01L25/065 ,  H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34

    Abstract: AN APPARATUS AND METHOD IS DISCLOSED THAT ALLOWS FOR THE ARRANGING IN A THREE DIMENSIONAL ARRAY SEMICONDUCTOR CHIPS ON A CIRCUIT BOARD(49). A UNIQUE CHIP CARRIER IS DISCLOSED ON WHICH ANY IC CHIP CAN BE POSITIONED ON ABOVE THE OTHER ON A CIRCUIT BOARD(49). ADDITIONALLY, THE CARRIER ALLOWS FOR THE TESTING OF IC CHIPS ON THE CARRIER AND UNDERNEATH IT WITHOUT HAVING TO REMOVE THE CARRIER AND CHIPS FROM THE SYSTEM EVEN IF THEY ARE OF THE BGA OR CSP TYPE. THE CARRIER INCLUDES EXPOSED TEST POINTS TO ALLOW AN ON SITE TEST.FIG. 1 & 2

    METHOD FOR FABRICATING A CIRCUIT BOARD WITH A THREE DIMENSIONAL SURFACE MOUNTED ARRAY OF SEMICONDUCTOR CHIPS
    8.
    发明专利
    METHOD FOR FABRICATING A CIRCUIT BOARD WITH A THREE DIMENSIONAL SURFACE MOUNTED ARRAY OF SEMICONDUCTOR CHIPS 未知

    公开(公告)号：MY131467A

    公开(公告)日：2007-08-30

    申请号：MYPI20023474

    申请日：2002-09-18

    Applicant: LEGACY ELECTRONICS INC

    Inventor： KLEDZIK KENNETH J

    IPC: H05K3/30

    Abstract: A METHOD AND APPARATUS FOR FABRICATING A THREE DIMENSIONAL ARRAY OF SEMICONDUCTOR CHIPS IS DISCLOSED. THE METHOD USES A MULTIPLE STEP FABRICATION PROCESS THAT AUTOMATES THE SURFACE MOUNTING OF SEMICONDUCTOR CHIPS WITH UNIQUE CHIP CARRIERS (21) TO ACHIEVE THE THREE DIMENSIONAL ARRAY OF CHIPS. THE METHOD INCLUDES A STEP OF DEPOSITING SOLDER ON A MULTITUDE OF CHIP CARRIERS AT ONE TIME, PLACING THE CHIP CARRIERS WITH CHIPS ON A PRINTED CIRCUIT BOARD (65) AND THEN RUNNING THE BOARD WITH CHIPS AND CARRIERS ARRANGED IN A THREE DIMENSIONAL ARRAY THROUGH A SINGLE REFLOW OVEN (87) TO COMPLETE A SINGLE REFLOW PROCESS TO PERMANENTLY CONNECT ALL OF THE COMPONENTS. THE APPARATUS INCLUDES A UNIQUE CHIP CARRIER PALLET (23) AND PRINT FIXTURE PEDESTAL (31) THAT WORK IN COMBINATION TO POSITION THE CHIP CARRIERS FOR THE AUTOMATIC DEPOSITION OF SOLDER ON A MULTITUDE OF CARRIERS AT ONCE AND THEN POSITION THEM FOR ADDITION TO THE CIRCUIT BOARD.(FIG 6)

    ELECTRONIC MODULE HAVING A THREE DIMENSIONAL ARRAY OF CARRIER-MOUNTED INTEGRATED CIRCUIT PACKAGES
    9.
    发明申请
    ELECTRONIC MODULE HAVING A THREE DIMENSIONAL ARRAY OF CARRIER-MOUNTED INTEGRATED CIRCUIT PACKAGES 审中-公开
    具有载体安装集成电路组件的三维尺寸阵列的电子模块

    公开(公告)号：WO0169680A2

    公开(公告)日：2001-09-20

    申请号：PCT/US0107926

    申请日：2001-03-13

    Applicant: LEGACY ELECTRONICS INC ,  KLEDZIK KENNETH J ,  ENGLE JASON C

    Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

    IPC: H01L25/18 ,  H01L25/10 ,  H01L25/11 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

    CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K3/0061 ,  H05K3/3405 ,  H05K3/3421 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/1034 ,  H05K2201/10515 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2201/10924 ,  H01L2924/00

    Abstract: A package carrier (100) for increasing the circuit density on printed circuit boards (503). The package carrier (100) mounts on a printed circuit board (503) on top of a first integrated circuit package (507) that is also mounted on the printed circuit board (503). The carrier (100) has an upper major surface (102U) having a pad array on which a second integrated circuit package (501) is mountable. The carrier (100) has a plurality of leads by means of which the carrier (100) is surface mounted to the printed circuit board (503). Each carrier lead is also electrically connected to a single pad of the pad array on the upper surface (102U). The integrated circuit package (507) beneath the carrier (100) shares all or most printed circuit board (503) connections in common with the carrier (100) and consequently the integrated ciurcut package (501) mounted upon the carrier (100). The carrier (100) also includes heat sink or heat disipation structures.

    Abstract translation: 一种用于增加印刷电路板（503）上的电路密度的封装载体（100）。 封装载体（100）安装在也安装在印刷电路板（503）上的第一集成电路封装（507）的顶部上的印刷电路板（503）上。 载体（100）具有具有垫阵列的上主表面（102U），其上可安装第二集成电路封装（501）。 载体（100）具有多个引线，载体（100）通过该引线表面安装到印刷电路板（503）。 每个载体引线也电连接到上表面（102U）上的焊盘阵列的单个焊盘。 载体（100）下方的集成电路封装（507）与载体（100）共同分享全部或大部分印刷电路板（503）连接，从而共同安装在载体（100）上的集成切割封装（501）。 载体（100）还包括散热器或散热结构。

Patent Agency Ranking