公开(公告)号：JPH09186286A

公开(公告)日：1997-07-15

申请号：JP12996

申请日：1996-01-05

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： OCHI TAKAO ,  FUNAKOSHI HISASHI ,  OKUMURA ICHIRO ,  HONMA FUTOSHI ,  OKUMA KEIJI ,  FUJIMOTO KEIICHI

IPC: H01L23/28 ,  H01L21/60 ,  H01L23/495 ,  H01L23/50

Abstract: PROBLEM TO BE SOLVED: To provide a lead frame for forming an LOC package with high reliability by making it possible to incorporate a semiconductor chip of large area in a standardized volume. SOLUTION: Connecting leads 3 extended from a lead frame body side to a semiconductor chip mounting area Retr side and support leads 4 are formed on the unit part for mounting the chip of a lead frame 10. A movable part 5 and spring 6A for elastically supporting the part 5 are provided between the leads 4 and the body. The end 4a of the lead 4 connected to the part 5 is extended inward of the area Retr in a natural state, and at the time of mounting the chip, the chip can be supported and fixed by the spring 6A in contact with the side of the chip. The stress or increase of the volume does not occur at a package without retaining the base end of the lead 4, the part 5 and the spring 6A in the package.

公开(公告)号：JP2000293653A

公开(公告)日：2000-10-20

申请号：JP9732299

申请日：1999-04-05

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： MAEDA KENJI ,  HONMA FUTOSHI ,  TAKADA TAKASHI

IPC: G06K19/077

Abstract: PROBLEM TO BE SOLVED: To provide an IC card in a resin sealed integral mold type whose mold releasing performance at the time of sealing can be satisfactorily held even when the number of electrode terminals is increased, and inter-electrode terminal intervals are made narrow, and to provide an IC card whose wrap due to resin contraction in the sealing is reduced. SOLUTION: In this IC card, the height of a partition part between each electrode terminal 2 is increased so that mold releasing performance at the time of sealing can be made satisfactory. Also, electrode terminals are arranged so as to be divided into plural parts so that inter-electrode terminal partition part 3 whose width and height are sufficiently ensured can be formed. Then, a resin layer formed at the same places on the opposite face of the electrode terminals is formed so as to be thin or eliminated so that warp of the IC card is reduced.

公开(公告)号：JPH04329653A

公开(公告)日：1992-11-18

申请号：JP10007991

申请日：1991-05-01

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： HONMA FUTOSHI

IPC: G01R31/26 ,  H01L21/66

Abstract: PURPOSE:To screen semiconductor devices for reliability before an assembly/ sealing or packaging step. CONSTITUTION:A proving test 11 is performed after a preprocess (wafer process). To age wafers for initial device defects, a burn-in step 12 is performed by giving electrical or thermal stress. An electrical test step 13 is performed to check the wafer for specified characteristics. The wafers accepted in the step 13 are transferred to an assembly/sealing step 14 and further to an electrical test step 15.

公开(公告)号：JP2000133748A

公开(公告)日：2000-05-12

申请号：JP30385798

申请日：1998-10-26

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： TAKADA TAKASHI ,  OCHI TAKAO ,  NARAOKA HIROKI ,  HONMA FUTOSHI ,  MAEDA KENJI

IPC: H01L21/56 ,  H01L23/12 ,  H01L23/28

Abstract: PROBLEM TO BE SOLVED: To surely ensure planarity of the lower surface of a wiring board by preventing the adhesion of a sealing resin to the lower surface, even through a resin package is provided on the side faces of the wiring board. SOLUTION: A semiconductor chip 102 is bonded to the upper surface of a hard wiring board 100A via an adhesive layer 101, and the electrode pads in the peripheral edge section of the chip 102 are connected electrically to the connecting electrodes in the peripheral edge section of the board 100A through bonding wires 103. On the lower surface of the board 100A, land-like outside connecting terminals 105A or ball-like outside connecting terminals 105B are formed. The terminals 105A or 105B are connected electrically to the connecting electrodes of the board 100A. The semiconductor chip 102, bonding wires 103, and the upper surface and side faces of the wiring board 100A are covered with a resin package 104, but the lower sections of the side faces of the board 100A are not covered with the package 104.

公开(公告)号：JP2000156462A

公开(公告)日：2000-06-06

申请号：JP32983998

申请日：1998-11-19

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： HONMA FUTOSHI ,  TAKADA TAKASHI ,  NARAOKA HIROKI

IPC: H01L25/18 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To obtain a thinner semiconductor integrated device which is high in productivity, low in cost, high in degree of freedom of chip design, capable of coping with a high-speed operation, and smaller in thickness than usual. SOLUTION: This semiconductor integrated device is equipped with a first semiconductor chip 10 whose element forming surface is fixed on the underside of a lead frame through a lead-on-chip, a second semiconductor chip 11 whose non-element forming surface is fixed to the top surface of a die pad 12 through an adhesive layer 16 without making its element forming surface or non-element forming surface confront that the first semiconductor chip 10, metal wires 17 and 18 which electrically connect the first semiconductor chip 10 and inter leads 13, and the second semiconductor chip 11 and inner leads 13 together respectively, and a sealing resin 19 which seals up the lead frame, semiconductor chips 10 and 11, and the metal wires 17 and 18.

公开(公告)号：JPH06120227A

公开(公告)日：1994-04-28

申请号：JP27128492

申请日：1992-10-09

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： HONMA FUTOSHI ,  IBARAKI AKIRA

IPC: H01L21/60 ,  H01L21/321

Abstract: PURPOSE:To enable sealing of highly precise LOC structure with high density wiring. CONSTITUTION:A bonding pad 2 constituted of a metal coating film is formed on a chip. A pad cap 3 composed of conductive material having a melting point higher than or equal to absolute maximum rated temperature is formed on the bonding pad 2. By fusing the pad cap 3 and again setting it up, a wire lead 6 is electrically connected with the bonding pad 2. As the result, when the interval of the bonding pad 2 is small, sealing or packaging of LOC structure is easily enabled.

公开(公告)号：JPH03257968A

公开(公告)日：1991-11-18

申请号：JP5719690

申请日：1990-03-08

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： HONMA FUTOSHI ,  IBARAKI AKIRA

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L29/78

Abstract: PURPOSE:To raise surge withstand voltage of a power supply terminal or an input terminal providing a MOS capacitor with its one end constructed with a diffusion region in contact with a diffusion region of a drain electrode of a transistor of a power supply protective circuit, and with its other end constructed with a gate electrode of a power supply protective transistor. CONSTITUTION:A MOS capacitor 23 is constructed with a diffusion region 15 with its one terminal sharing a gate electrode 11 of a transistor 21 and with its other terminal in contact with a drain diffusion region 9 of the transistor 21, and being of the same potential and a drain potential. The transistor constituting a protective circuit includes a capacitor 23, whereby high voltage applied to a power supply terminal 1 can be discharged without substantially increasing a layout area and without being subjected to thermal damage of the transistor 21.