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    SEMICONDUCTOR PACKAGE, ITS MANUFACTURE, AND CONVEYANCE FRAME
    2.
    发明专利
    SEMICONDUCTOR PACKAGE, ITS MANUFACTURE, AND CONVEYANCE FRAME 失效

    公开(公告)号：JP2000133748A

    公开(公告)日：2000-05-12

    申请号：JP30385798

    申请日：1998-10-26

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： TAKADA TAKASHI ,  OCHI TAKAO ,  NARAOKA HIROKI ,  HONMA FUTOSHI ,  MAEDA KENJI

    IPC: H01L21/56 ,  H01L23/12 ,  H01L23/28

    Abstract: PROBLEM TO BE SOLVED: To surely ensure planarity of the lower surface of a wiring board by preventing the adhesion of a sealing resin to the lower surface, even through a resin package is provided on the side faces of the wiring board. SOLUTION: A semiconductor chip 102 is bonded to the upper surface of a hard wiring board 100A via an adhesive layer 101, and the electrode pads in the peripheral edge section of the chip 102 are connected electrically to the connecting electrodes in the peripheral edge section of the board 100A through bonding wires 103. On the lower surface of the board 100A, land-like outside connecting terminals 105A or ball-like outside connecting terminals 105B are formed. The terminals 105A or 105B are connected electrically to the connecting electrodes of the board 100A. The semiconductor chip 102, bonding wires 103, and the upper surface and side faces of the wiring board 100A are covered with a resin package 104, but the lower sections of the side faces of the board 100A are not covered with the package 104.

    IC CARD
    3.
    发明专利
    IC CARD 失效

    公开(公告)号：JP2000293653A

    公开(公告)日：2000-10-20

    申请号：JP9732299

    申请日：1999-04-05

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： MAEDA KENJI ,  HONMA FUTOSHI ,  TAKADA TAKASHI

    IPC: G06K19/077

    Abstract: PROBLEM TO BE SOLVED: To provide an IC card in a resin sealed integral mold type whose mold releasing performance at the time of sealing can be satisfactorily held even when the number of electrode terminals is increased, and inter-electrode terminal intervals are made narrow, and to provide an IC card whose wrap due to resin contraction in the sealing is reduced. SOLUTION: In this IC card, the height of a partition part between each electrode terminal 2 is increased so that mold releasing performance at the time of sealing can be made satisfactory. Also, electrode terminals are arranged so as to be divided into plural parts so that inter-electrode terminal partition part 3 whose width and height are sufficiently ensured can be formed. Then, a resin layer formed at the same places on the opposite face of the electrode terminals is formed so as to be thin or eliminated so that warp of the IC card is reduced.

    LEAD FRAME
    4.
    发明专利
    LEAD FRAME 失效

    公开(公告)号：JPH11233707A

    公开(公告)日：1999-08-27

    申请号：JP3279798

    申请日：1998-02-16

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： MAEDA KENJI ,  TAKADA TAKASHI

    IPC: B21F1/00 ,  H01L21/56 ,  H01L23/50

    Abstract: PROBLEM TO BE SOLVED: To prevent exposure of a semiconductor chip, bonding wires, etc., and generation of voids, by forming bent parts bent in a lead frame thickness direction on a supporting lead. SOLUTION: A semiconductor chip is mounted on a die pad 1 via a pellet fixing member such as adhesive agent, and electrodes of the semiconductor chip are bonded to inner leads 4 of a lead frame by using wires such as gold wires. After molding is performed with resin such as epoxy resin, outer leads 6 are formed. In this lead frame, bent parts 2a are formed in a frame thickness direction on both sides of a supporting lead 2, so that change of flowing balance of fused resin is generated. Thereby the supporting lead 2 is hardly deflected when pressure of resin is applied superfluously to members in a package such as the semiconductor chip and the die pad 1, and vertical movement of the semiconductor chip and the die pad 1 can be restrained.

    WIRE BONDING METHOD AND PRESSING TOOL USING THE SAME
    5.
    发明专利
    WIRE BONDING METHOD AND PRESSING TOOL USING THE SAME 失效

    公开(公告)号：JPH11168119A

    公开(公告)日：1999-06-22

    申请号：JP33520797

    申请日：1997-12-05

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： MAEDA KENJI ,  INUI TADAHISA

    IPC: H01L21/60

    Abstract: PROBLEM TO BE SOLVED: To stabilize a tail length, regardless of the lead height on a second bond side. SOLUTION: In a state in which a wire 4 is nipped by a wire clamper 1 after end of a second bonding step, the wire 4 is cut from a lead 8. Thereafter, the wire clamper 1 and a capillary tool 2 are lifted up and a space between the wire clamper 1 and the capillary tool 2 is narrowed, thereby the wire 4 is led out by a specified tail length from the capillary tool 2. In this step, the wire 4 ends up being surely cut at a the tip of the capillary tool 2. A space between the wire clamper 1 and the capillary tool 2 is narrowed, whereby the wire 4 is led out by a specified tail length from the capillary tool 2. Therefore, even when there are variations in the height of the lead 8, there with be no variation in the specified tail length, and a diameter of a ball 5 formed in a tail 10 is fixed and satisfactory bonding can be made.

    LEAD FRAME AND ITS MANUFACTURE, AND SEMICONDUCTOR DEVICE USING THE LEAD FRAME
    6.
    发明专利
    LEAD FRAME AND ITS MANUFACTURE, AND SEMICONDUCTOR DEVICE USING THE LEAD FRAME 失效

    公开(公告)号：JPH11150161A

    公开(公告)日：1999-06-02

    申请号：JP31540597

    申请日：1997-11-17

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： MAEDA KENJI

    IPC: H01L21/60 ,  H01L23/28 ,  H01L23/50

    Abstract: PROBLEM TO BE SOLVED: To enable a lead frame to be manufactured at low price through conventional manufacturing technology, and make it applicable to a semiconductor element where an electrode pad is arranged in the vicinity of the element too, and furthermore to downsize it nearly to a semiconductor element size. SOLUTION: A lead pattern in which a suspension lead 8 and a terminal part 10 are connected to the outer frame 9 of a lead is made, and one side of a both-sided adhesive tape 3 is stuck to the suspension lead 8 and the terminal part 10, and the terminal part 10 is chemically etched and punched by pressing to form an independent terminal 12 and make a lead frame 11. Using this lead frame 11, the other side of both-sided adhesive tape 3 of the lead frame 11 is stuck to the circuit formation fact of the semiconductor element 4, and the independent terminal 10 of the lead frame 11 and the electrode pad 5 of the semiconductor element 4 are connected electrically by a wire 6, and a part of the independent terminal 10 is exposed, and the semiconductor element 4 and the lead frame 11 are encapsulated with a package 7.

    SOCKET FOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    7.
    发明专利
    SOCKET FOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH10256437A

    公开(公告)日：1998-09-25

    申请号：JP5577497

    申请日：1997-03-11

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： MAEDA KENJI

    IPC: H01L23/32 ,  H01R33/76

    Abstract: PROBLEM TO BE SOLVED: To suppress the coplanarity of a semiconductor device as small as possible by the result of the steps, which suppress the deformation of the semiconductor device to the small degree, or prevent the deformation perfectly. SOLUTION: A socket main body 1, supporting points 3 and 4 for supporting the both ends and the central part of the semiconductor device, and contacts 2 and contact terminals 5 are provided. The force in the vertical lower direction is applied on the semiconductor device mounted on a socket for the semiconductor. Furthermore, the semiconductor device is supported by the supporting points 3 at both ends. Therefore, a resin part 6 indicates the inclination of the deformation of the protrusion in downward under the state wherein the resin part 7 of the semiconductor device is softened at the high temperature especially in burn-in time. Since the supporting point 4 for supporting the central part is provided in addition to the supporting points 3 for supporting the both end parts of the semiconductor, however, the deformation of the resin part 7 of the semiconductor device can be suppressed within some degree. Therefore, when the semiconductor device is mounted on a printed wiring board, the contact of the electrode part of the printed wiring board and an outer lead 6 of the semiconductor device becomes secure.

    LEAD FRAME
    8.
    发明专利
    LEAD FRAME 失效

    公开(公告)号：JPH11121681A

    公开(公告)日：1999-04-30

    申请号：JP28647097

    申请日：1997-10-20

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： MAEDA KENJI

    IPC: H01L23/50

    Abstract: PROBLEM TO BE SOLVED: To eliminate the dispersion of the heights of lead tip parts in respective leads without adjustment and re-manufacture, after a lead-bending metallic mold is manufactured at forming of the step form of a down set and the like on a lead frame. SOLUTION: In a lead frame, in which the step forms are formed by the bending work of the lead and plural leads 1-3 whose lengths from step-form forming parts to lead tip parts differ, lead cross-sectional areas in the step-form forming parts are adjusted smaller, the longer the lengths are from the step-form forming parts to the lead tip parts. The spring back quantity of the bending part is adjusted, and the heights of the lead tip parts are made to be constant.

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