公开(公告)号：JP2000049229A

公开(公告)日：2000-02-18

申请号：JP20555399

申请日：1999-07-21

Applicant: MOTOROLA INC

Inventor： GREGOR BRACKELMAN ,  RAMUNAS BENKATORAMAN ,  MATTHEW THOMAS HERICK ,  CINDY R SIMPSON ,  FIORDALICE ROBERT W ,  DENNING DEAN J ,  JAIN AJAY ,  CHRISTIANO CAPASO

IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/82 ,  H01L23/485 ,  H01L23/52 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a mutual connection structure in a semiconductor device that has advantages as compared with prior art and the method for forming the same. SOLUTION: A mutual connection part 60 is formed on a substrate 10. In an embodiment, an adhesive/barrier layer 81, a copper alloy seed layer 42 and a copper film 43 are deposited on the substrate 10, and the substrate 10 is annealed. In an alternative embodiment, the copper film is deposited on the substrate and the copper film is annealed. Furthermore, in another embodiment, the adhesive/barrier layer 81, a seed layer 82, a conductive film 83 and a copper alloy capping film 84 are deposited on the substrate 10 to form a mutually connecting part 92. The stages of depositing and annealing are performed on a common processing platform.

公开(公告)号：JP2000323436A

公开(公告)日：2000-11-24

申请号：JP2000051583

申请日：2000-02-28

Applicant: MOTOROLA INC

Inventor： DENNING DEAN J ,  GARCIA SAM S ,  SMITH BRADLEY P ,  LOOP DANIEL J ,  HAMILTON GREGORY NORMAN ,  ISLAM MOHAMMED RABIUL ,  BRIAN G ANTHONY

IPC: C23C14/14 ,  C23C14/34 ,  C23C14/50 ,  C23C14/56 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To manufacture a great amount of copper interconnection parts at lower costs, and enhance yield and reliability by a method wherein power for both a sputtering target and a coil is controlled between the stacks of barrier layers. SOLUTION: After a wafer is disposed in a chamber 40 and the chamber is stabilized, power of, for example, 1000 W is applied on a target 48, and this power is continuously applied between the stacks of barrier layers. First, power of, for example, about 1000 W is supplied to the target 48, and substantially simultaneously power of, for example, about 1500 W is supplied to a coil 52. Namely, an initial part of the barrier film is deposited between high coil powering sequences, and the other part of the barrier film is deposited between low coil power or zero coil powering sequences. Accordingly, the power to the coil is selectively controlled between the stacks of the barrier film, whereby it is possible to design the stress of the barrier film in accordance with each stress of upside and downside layers.

公开(公告)号：JPH10284717A

公开(公告)日：1998-10-23

申请号：JP10041098

申请日：1998-03-27

Applicant: MOTOROLA INC

Inventor： ORUBANMI ORUFUEMI ADETSUTSU ,  DENNING DEAN J ,  JAMES D HEYDEN ,  CHITORA K SABURAMANIAN ,  AAKARUGADO R SHITARAM

IPC: H01L29/43 ,  C23C16/44 ,  C23C16/455 ,  H01L21/02 ,  H01L21/205 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To enable the formation of a metal semiconductor, without requiring special processes or substances by controlling the increase in thickness and change of dielectric constant of a gate dielectric layer, thus preventing the increase in the thickness of the gate dielectric layer, and causing the metal semiconductor layer to have good adhesiveness to the gate dielectric layer, since fluorine causes increases in the thickness of the gate dielectric layer and the change of dielectric constant of the gate dielectric layer in the manufacture of a semiconductor having a metalsemiconductor layer. SOLUTION: A metal semiconductor layer 26 is formed on an insulating layer 20, thereby gradually changing the quantity of semiconductor and metals across the metal semiconductor layer 26. In this case, the metal semiconductor layer 26 has a relatively high silicon concentration near its upper surface and bottom surface. In other cases, a metal-semiconductor-nitride layer contains nitrogen near its bottom surface and contains substantially no nitrogen near its upper surface. The layer 26 is formed by using chemical vapor deposition or sputtering.

公开(公告)号：JP2001230256A

公开(公告)日：2001-08-24

申请号：JP2001018587

申请日：2001-01-26

Applicant: MOTOROLA INC

Inventor： JIMING ZANG ,  DENNING DEAN J ,  GARCIA SAM S ,  SCOTT K PODDER

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide an inlaid mutual connection structure whose bonding property between a conductor and a dielectric material is improved. SOLUTION: Bonding property of a barrier layer to a foundation dielectric is improved by forming a bonding/interlaminar region (410) of a semiconductor substrate element (404) before deposition of a barrier layer (412), strength to the next mutual connection layer is improved without changing function of a barrier layer, and diffusion of Cu into a dielectric substrate is limited. A bonding/interlaminar region is formed inside inlaid structures (400, 500) of a semiconductor wafer. The inlaid structure is connected to upper and lower metallic layers through a via extending to a copper layer inside a dielectric layer. When a bonding/interlaminar region is formed, treatment gas is made to flow in a glow discharge process of a dielectric substrate. A barrier layer and a bonding/interlaminar region can be formed inside an inlaid structure of a semiconductor wafer. Gas or the like comprising nitrogen, hydrogen and carbon atom is used as treatment gas.

公开(公告)号：JPH1174227A

公开(公告)日：1999-03-16

申请号：JP20119798

申请日：1998-07-01

Applicant: MOTOROLA INC

Inventor： JIMING ZAN ,  DENNING DEAN J ,  LARRY E FRIESA ,  HAKKU-REI CHAN

IPC: H01L21/285 ,  H01L21/203 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To accurately realize a semiconductor device having interconnection, including a barrier film and a conductive film, with a simple process. SOLUTION: A semiconductor device has a continuously changing portion 1032 of a first film like a barrier film used in a conductive structure such as interconnection and a conductive plug. The continuously changing portion contains a first element and a second element like a refractory metal and nitrogen. The continuous change includes a change in the concentration of the first element near more conductive second films 1054 and 1064. Another semiconductor device includes a first conductive film and second conductive films 1054 and l065, made mainly of copper. The first conductive film has a first portion, a second portion and a third portion. The third portion is closest to the second conductive film. The concentration of nitrogen in the second portion is higher than the concentration of nitrogen in the first or third portions.

公开(公告)号：AU7597301A

公开(公告)日：2002-02-05

申请号：AU7597301

申请日：2001-07-18

Applicant: MOTOROLA INC

Inventor： ARUNACHALAM VALLI ,  VENTZEK PETER L G ,  RAUF SHAHID ,  DENNING DEAN J ,  ZHANG JIMING

IPC: H01L21/768

公开(公告)号：WO0209149A3

公开(公告)日：2002-05-16

申请号：PCT/US0122566

申请日：2001-07-18

Applicant: MOTOROLA INC

Inventor： ARUNACHALAM VALLI ,  VENTZEK PETER L G ,  RAUF SHAHID ,  DENNING DEAN J ,  ZHANG JIMING

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76862 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873

Abstract: A method for improving the conformality and optimizing step coverage in semiconductor features (200) such as vias (200) and trenches is described herein. By performing an additional sputtering step after at least part of the metal (250) has been deposited on a wafer feature, undesirably thick metal. deposits near the top and at the bottom of a feature (200) can be reduced. By reducing the overhang at the top of a feature (200) such as a via (200), it is easier for metal species to reach and be deposited on the sidewalls. By reducing the thickness of deposited metal at the bottom of a via (200), via (200) resistance can be decreased. The extra sputtering step may be performed a single time after all metal has been deposited. Alternatively, a small amount of metal may be deposited, a sputtering step may be performed, more metal may be deposited, and additional sputtering steps can be performed.

Abstract translation: 本文描述了用于改进半导体特征（200）（例如通孔（200）和沟槽）中的共形性和优化阶梯覆盖的方法。 在金属（250）的至少一部分沉积在晶片特征上之后，通过执行额外的溅射步骤，不合需要的厚金属。 可以减少特征（200）的顶部和底部附近的沉积物。 通过减少诸如通孔（200）的特征（200）的顶部处的悬突，金属物质更容易到达并沉积在侧壁上。 通过减小通孔（200）底部的沉积金属的厚度，可以减小（200）电阻。 在所有金属已经沉积之后，额外的溅射步骤可以执行一次。 或者，可以沉积少量的金属，可以执行溅射步骤，可以沉积更多的金属，并且可以执行额外的溅射步骤。