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公开(公告)号：DE60116742T2
公开(公告)日：2006-10-26
申请号：DE60116742
申请日：2001-02-23
Applicant: QUALCOMM INC
Inventor： SIH C , CHEN XUFENG , HSU D
Abstract: Two multiply-accumulate units are coupled together so that the computation (B*C)+(D*E) can be completed in one cycle. An adder (216) adds together the products of the two multipliers (206), (208). The sum is applied to the first accumulator (220). Preferably, the second product is also applied to the second accumulator (222), and a multiplexer (218) applies either a zero or the second product to the adder (216). If two unrelated computations are to be executed simultaneously, then the zero is applied, and the output of the second accumulator is fed back to the register file (PI2). If a single (B*C)+(D*E) computation is to be executed, then the second product is applied to the adder, and the output of the second accumulator is disregarded.
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公开(公告)号：DE69924867T2
公开(公告)日：2006-03-02
申请号：DE69924867
申请日：1999-11-18
Applicant: QUALCOMM INC
Inventor： ZOU QUIZHEN , SIH C , AGRAWAL AVNEESH
Abstract: A novel and improved method and apparatus for a fast-slewing pseudorandom noise sequence generator is described. One or more loadable PN generators are controlled by a DSP or microprocessor in conjunction with a free-running counter which maintains a reference offset count. The PN generator will typically be part of a finger or searcher. The DSP or microprocessor may assist in other finger or searcher functions as well as the slew function, and can control one or more fingers and/or searchers. Each PN generator is comprised of a loadable linear feedback shift register (LFSR) or its equivalent, a loadable counter for maintaining an index of the state of that particular PN generator, and a slew control device capable of receiving a slew command and controlling the LFSR and index counter to enact an advance or a retard of a certain offset distance.
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公开(公告)号：DE69919729T2
公开(公告)日：2005-09-29
申请号：DE69919729
申请日：1999-09-03
Applicant: QUALCOMM INC
Inventor： KANG INYUP , SIH C , ZOU QIUZHEN
Abstract: The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment of the invention comprises a method for performing position location comprising the steps of receiving signal samples, generating a coarse acquisition sequence, rotating the coarse acquisition sequence yielding a rotated coarse acquisition sequence, and applying the rotated coarse acquisition sequence to the signal samples at a set of time offsets yielding correlated output data.
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公开(公告)号：DE69925720D1
公开(公告)日：2005-07-14
申请号：DE69925720
申请日：1999-03-04
Applicant: QUALCOMM INC
Inventor： SIH C , ZOU QUIZHEN , JHA K , KANG INYUP , LIN JIAN , MOTIWALA QUAEED , JOHN DEEPU , ZHANG LI , ZHANG HAITAO , LEE WAY-SHING , SAKAMAKI E , KANTAK A
Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).
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公开(公告)号：DE69431923T2
公开(公告)日：2003-11-06
申请号：DE69431923
申请日：1994-10-27
Applicant: QUALCOMM INC
Abstract: An apparatus that automatically adjusts the adaptation block size for a least-mean square (LMS) adaptive filter depending on the input signal-to-noise ratio (SNR) is disclosed. The apparatus monitors the instantaneous SNR and continually adjusts the block size to provide high noise immunity, thereby increasing the convergence speed of the filter and decreasing the asymptotic mean-square error. An exemplary embodiment of the present invention is presented in the context of acoustic echo cancellation, though it is noted that the adaptive filter of the present invention is useful in any environment in which the noise characteristics are subject to change.
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Patent Agency Ranking
公开(公告)号：DE69934706T2
公开(公告)日：2007-10-18
申请号：DE69934706
申请日：1999-10-12
Applicant: QUALCOMM INC
Inventor： BUTLER K , ZHANG HAITAO , TIEDEMANN G , ZOU QIUZHEN , SIH C , AGRAWAL AVNEESH
IPC: H04W24/02 , H04B1/7075 , H04B1/7077 , H04B1/7115 , H04W52/02
Abstract: A novel and improved method for performing paging is described. In one embodiment of the invention a searcher is used to detect spread spectrum signals. Samples received RF signals are stored in a sample buffer. During standby mode, the samples are gathered during paging slots assigned to the mobile. A set of searches are performed on the samples, and if pilot signals are detected additional demodulation is performed to detect paging messages. The resulting set of demodulation data may be combined to increase detection. After a page message has been detected, additional demodulation resources may be activated to processes more complete page messages, or other information channels. In one embodiment of the invention, the searcher includes a demodulator to perform quick page detection without the use of finger elements to reduce idle mode power consumption.
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公开(公告)号：DE69735635T2
公开(公告)日：2007-05-03
申请号：DE69735635
申请日：1997-11-13
Applicant: QUALCOMM INC
Abstract: A novel and improved method and apparatus for providing an interface to a digital wireless telephone system compatible with standard analog wire line telephones and analog wire line fax machines is disclosed. During a telephone call, a fax detector (11) monitors the incoming data for fax signals. If a fax is detected, the data processor (12) switches from processing the data as if it were voice to processing it as fax. In addition, the remote station is sent a signal notifying it to process the data as fax rather than voice. The fax detector (11) operates by detecting the preamble of a V.21 message, present at the beginning of every fax call. Energy is measured in both frequencies of the BFSK signals. A decision is made by analyzing these energies and locating a specific pattern which repeats itself a sufficient number of times.
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公开(公告)号：DE69916255T2
公开(公告)日：2005-04-14
申请号：DE69916255
申请日：1999-02-03
Applicant: QUALCOMM INC
Inventor： SIH C , BI NING C O QUALCOMM INCORPORA
IPC: G10L21/0208 , G10L15/02 , G10L15/06 , G10L15/10 , G10L15/20 , G10L21/0216
Abstract: The speech recognition training unit is modified to store digitized speech samples into a speech database that can be accessed at recognition time. The improved recognition unit comprises a noise analysis, modeling, and synthesis unit which continually analyzes the noise characteristics present in the audio environment and produces an estimated noise signal with similar characteristics. The recognition unit then constructs a noise-compensated template database by adding the estimated noise signal to each of the speech samples in the speech database and performing parameter determination on the resulting sums. This procedure accounts for the presence of noise in the recognition phase by retraining all the templates using an estimated noise signal with similar characteristics as the actual noise signal that corrupted the word to be recognized. This method improves the likelihood of a good template match, which increases the recognition accuracy.
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公开(公告)号：DE60116742D1
公开(公告)日：2006-04-06
申请号：DE60116742
申请日：2001-02-23
Applicant: QUALCOMM INC
Inventor： SIH C , CHEN XUFENG , HSU D
Abstract: Two multiply-accumulate units are coupled together so that the computation (B*C)+(D*E) can be completed in one cycle. An adder (216) adds together the products of the two multipliers (206), (208). The sum is applied to the first accumulator (220). Preferably, the second product is also applied to the second accumulator (222), and a multiplexer (218) applies either a zero or the second product to the adder (216). If two unrelated computations are to be executed simultaneously, then the zero is applied, and the output of the second accumulator is fed back to the register file (PI2). If a single (B*C)+(D*E) computation is to be executed, then the second product is applied to the adder, and the output of the second accumulator is disregarded.
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公开(公告)号：DE69925720T2
公开(公告)日：2006-03-16
申请号：DE69925720
申请日：1999-03-04
Applicant: QUALCOMM INC
Inventor： SIH C , ZOU QUIZHEN , JHA K , KANG INYUP , LIN JIAN , MOTIWALA QUAEED , JOHN DEEPU , ZHANG LI , ZHANG HAITAO , LEE WAY-SHING , SAKAMAKI E , KANTAK A
Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).
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